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Programming Interface Information:
The Monitor Records are intended Programming Interfaces that allow the customer to write programs to obtain services of z/VM. |
MRMTRCCC
PrologControl Block Contents
Cross Reference
MRMTRCCC Prolog
DSECT NAME - MTRCCC
FUNCTION - Map a Monitor record.
LOCATED By -
Through the Monitor Control Area
REFERENCED CONTROL BLOCKS -
MRRECHDR Monitor Record Header
NAME - MRMTRCCC
DESCRIPTIVE NAME - Monitor Event Record
Domain 1 - Monitor Domain
Record 18 - CPU Capability Change
DESCRIPTION - Record of a CPU Capability Change reported by
the Support Element.
NOTES:
1. For additional information about the format and
meaning of the MTRCCC_STSI111 field, refer to the
following book:
- Principles of Operation for the layout of the
STSI 1.1.1 output (first 180 bytes) which is
documented in Chapter 10 under "STORE SYSTEM
INFORMATION". The field meanings are there also.
2. When a field in this record uses the term "CPU/core",@VRKP3VV
the meaning of the field changes based on whether
Multithreading (MT) is enabled for this partition.
Refer to Monitor Sample Record Domain 1 Record 4
(MRMTRSYS) to determine whether MT is enabled for
this partition as well as the number of threads for
each CPU type.
When MT is not enabled, a physical core
contains only one CPU:
- CPU : central processing unit.
- CORE : physical unit containing one CPU.
In this environment the core has
1 thread, the term "thread" is not used,
and the term "CPU" is generally favored
over the term "core".
When MT is enabled, a physical core contains one or
more CPUs (aka "threads"):
- CPU : central processing unit. Identified by
CPU address which consists of core ID
and thread ID.
- CORE : physical unit containing one or more CPUs
(aka "threads"). All CPUs of a core have
the same CPU type.
- THREAD: synonym for a CPU that is a member of a
core. Each thread on a core has a
distinct thread ID (TID), numbered from
0 up to the maximum thread ID available
on the core.
MRMTRCCC Control Block Contents
Offsets Dec Hex Type Len Name (Dim) Description 0 0 Structure 236 MTRCCC Start of monitor record 0 0 Character 0 MTRCCC_MRHDR Record header - see MRRECHDR for details 0 0 Character 20 MRHDR 0 0 Unsigned 2 MRHDRLEN 2 2 Unsigned 2 MRHDRZER 4 4 Unsigned 1 MRHDRDM 5 5 Unsigned 1 * 6 6 Unsigned 2 MRHDRRC 8 8 Character 8 MRHDRTOD 16 10 Character 4 * 20 14 Character 0 MRHDR_END 20 14 Unsigned 4 MTRCCC_CPUCAPAB STSI 1.2.2 field. The capability of a general CPU/core in the configuration in integer format. Used as an indication of the capability of the CPU/core relative to the capability of other processor models. When zero, all CPUs of any CPU type in the configuration have the same capability, as specified by the CPU capability, MTRCCC_CPUCAPAB. 24 18 Unsigned 4 MTRCCC_SCPCAPAB STSI 1.2.2 field. The capability of a specialty CPU/core in the configuration in integer format. Used as an indication of the capability of the CPU/core relative to the capability of other processor models. When zero, all CPUs of any CPU type in the configuration have the same capability, as specified by the CPU capability, MTRCCC_CPUCAPAB. 28 1C Unsigned 4 MTRCCC_NCPCAPAB STSI 1.2.2 field. The nominal capability of a general CPU/core in the configuration in integer format. When zero, this means the system is not operating at reduced speed, so the primary capability, MTRCCC_CPUCAPAB, value applies. 32 20 Unsigned 1 MTRCCC_SYSCCR Capacity-Change Reason. 33 21 Unsigned 1 MTRCCC_SYSCAI Capacity-Adjustment Indication. 34 22 Bitstring 1 MTRCCC_SSI1FLGS Miscellaneous flags. 1... .... MTRCCC_SSI1TRNS Transient CCR and CAI. .1.. .... * ..1. .... * ...1 .... * .... 1... * .... .1.. * .... ..1. * .... ...1 * 35 23 Unsigned 1 * RESERVED and available for IBM use. 36 24 Character 180 MTRCCC_STSI111 First 180 bytes of the STSI 1.1.1 output. 216 D8 Unsigned 4 MTRCCC_RCCCCAPF STSI 1.2.2 field. Specifies the capability of a general CPU/core in the current configuration in binary floating point (BFP) format. Used as an indication of the capability of the CPU/core relative to the capability of other processor models. 220 DC Unsigned 4 MTRCCC_RCCSCAPF STSI 1.2.2 field. Specifies the capability of a specialty CPU/core in the configuration in Binary Floating Point (BFP) format. Used as an indication of the capability of a CPU/core relative to the capability of other processor models. When zero, all CPUs of any CPU type in the configuration have the same capability, as specified by the CPU capability, MTRCCC_RCCCCAPF. 224 E0 Unsigned 4 MTRCCC_RCCNCAPF STSI 1.2.2 field. The nominal capability of a CPU/core in the configuration in Binary Floating Point Format. When zero, this means the system is not operating at reduced speed, so the primary capability, MTRCCC_RCCSCAPF, value applies. 0 0 228 E4 Unsigned 4 MTRCCC_RCCSPCP CP CPU speed. When not zero, contains a 32-bit unsigned binary integer which is the approximate number of CPU cycles per microsecond. 232 E8 Unsigned 4 MTRCCC_RCCSPSPC Specialty engine CPU speed. When not zero, contains a 32-bit unsigned binary integer which is the approximate number of CPU cycles per microsecond. 236 EC Character 0 MTRCCC_END
MRMTRCCC Cross Reference
Hex Hex
Name Offset Length Value
MRHDR 0 20
MRHDR_END 14 0
MRHDRDM 4 1
MRHDRLEN 0 2
MRHDRRC 6 2
MRHDRTOD 8 8
MRHDRZER 2 2
MTRCCC 0 236
MTRCCC_CPUCAPAB 14 4
MTRCCC_END EC 0
MTRCCC_MRHDR 0 0
MTRCCC_NCPCAPAB 1C 4
MTRCCC_RCCCCAPF D8 4
MTRCCC_RCCNCAPF E0 4
MTRCCC_RCCSCAPF DC 4
MTRCCC_RCCSPCP E4 4
MTRCCC_RCCSPSPC E8 4
MTRCCC_SCPCAPAB 18 4
MTRCCC_SSI1FLGS 22 1
MTRCCC_SSI1TRNS 22 80
MTRCCC_STSI111 24 180
MTRCCC_SYSCAI 21 1
MTRCCC_SYSCCR 20 1
This information is based on z/VM V6R4.0.
Last updated on 4 Oct 2016 at 15:11:18.
Copyright IBM Corporation, 1990, 2016