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Hex Dec Type/Val Lng Label (dup) Comments
---- ---- --------- ---- -------------- --------
0000 0 Structure SEG64 SEGMENT TABLE ENTRY
00000014 SEGGSHFT 20 Bits to shift by to convert
between segment number and
virtual address.
00000800 SEGGPTUN 2048 Number of bytes in a
page-table
0000000B SEGGPTUS 11 Number of bits to shift left
in order to multiply by SEGGPTUN.
00000009 SEGGPXDS 12-3 Bits to shift to convert
between an isolated page index
and the displacement into the
page table of the applicable 8
byte PTE.
When an invalid STE is associated with a paged-out PPGMBK,
the bytes 3-6, bits 30-55, of the invalid STE contain a PTRM
"virtual address" (PTRM address space index, segment index,
and page index, no byte index) of the form:
STE byte# ____3____ ____4____ ____5____ ____6____ ____7____
... xxxx xxAA AAAA ASSS SSSS SSSS PPPP PPPP xxxx xxxx
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STE bit# 30 37 48 55
where:
AAAAAAA = PTRM address space index
SSSSSSSSSSS = PTRM segment index within space
PPPPPPPP = PTRM page index within space
Or expressed as a 64-bit mask: X'00000003FFFFFF00':
.... ..11 SEGGPTRMH X'00000003' Isolate PTRM vaddr -
High
00FFFF00 SEGGPTRML X'FFFFFF00' Isolate PTRM vaddr -
Low
00000008 SEGGPTRM 8 Bits to shift to determine if
an invalid STE contains a PTRM
virtual address. Note that this
should be a 64-bit shift (SRAG),
as the PTRM address occupies both
words of the STE
00000008 SEGGPXNUM 8 Number of bits in a PX
1111 1111 SEGGPXRIT X'FF' Mask to isolate a right-
justified PX
64-bit mask X'FFFFFFFFFFFFFF800'
00FFFFFF SEGGPTMH X'FFFFFFFF' Isolate page-table
origin - High
00FFF800 SEGGPTML X'FFFFF800' Isolate page-table
origin - Low
0000F800 SEGGPTMLL X'F800' Isolate PTO - LowLow
64-bit mask X'FFFFFFFF80000000'
00FFFFFF SEGG2GMH X'FFFFFFFF' Isolate STE bits
which must be zero in a <2G
STE - High
.... .... SEGG2GML X'80000000' Isolate STE bits
which must be zero in a <2G
STE - Low
generate using equate names:
11.1 .... SEGGMBZA X'000000D0' Isolate STE bits
which must be zero in all z/VM
host STEs including both
architecturally reserved must be
zero bits as well as other bits
(such as SEGGCOMMN) which must be
0 - Low word only
64-bit mask X'0000000000000200'
32-bit high X'00000000'
00000200 SEGGPROM X'00000200' Isolate segment page
protect bit
64-bit mask X'0000000000000020'
32-bit high X'00000000'
..1. .... SEGGINVM X'00000020' Isolate invalid bit
64-bit mask X'0000000000000010'
32-bit high X'00000000'
...1 .... SEGGCOMM X'00000010' Isolate
common-segment bit
0000 0 Dbl-Word 8 SEGGENTR Segment table entry
00000008 SEGGLEN *-SEGGENTR Length of one STE
00000003 SEGGSzShf 3 Shift to multiply by size
0008 8 Dbl-Word 8 SEGGNEXT (0) Next segment table entry
0000 0 Signed 4 SEG64W0 (0) Word 0 of STE Bits 00-31 of STE
0000 0 Bitstring 1 SEG64B0 Byte 0 of STE Notes : The
following byte 0 flag bit
definitions are software
definitions and are therefore
only usable when the STE is known
to be invalid.
1... .... SEGGSTBL X'80' SEGGSTBL Bit 00 A system
reset function occurred while the
PGMBK was paged out. This bit
indicates that the PGSTE entries
for this segment must all be set
to stable state when the PGMBK is
next paged in. This bit only has
meaning when SEGGINVL=1
.... .1.. SEGGTRAN X'04' SEGGTRAN Bit 05 Segment is
being translated This bit is used
by software to serialize segment
translation. SEGGINVL must be =
1. This bit is a non-architected
software definition.
.... ..1. SEGGWAIT X'02' SEGGWAIT Bit 06 Segment has
translation requests waiting.
SEGGINVL must be = 1. In order to
enqueue a deferred STE
serialization request, CS must be
used to insist that both SEGGINVL
and SEGGTRAN are on continuously
while either turning SEGGWAIT on,
or finding it on and leaving it
on. This bit is a non-architected
software definition.
0001 1 Bitstring 1 SEG64B1 Byte 1 of STE
0002 2 Bitstring 1 SEG64B2 Byte 2 of STE
0003 3 Bitstring 1 SEG64B3 Byte 3 of STE
0004 4 Signed 4 SEG64W1 (0) Word 1 of STE Bits 32-63 of STE
0004 4 Bitstring 1 SEG64W10 Bits 32-39 of PTO or SFAA
0005 5 Bitstring 1 SEG64W11 Bits 40-47 of PTO or Bits 40-43
of SFAA, plus
are reserved by architecture,
must be zero in all Format 1
STEs
.... ...1 SEGGAV X'01' Bit 47 is the ACCF-Validity
control in Format 1 STEs
0006 6 Bitstring 1 SEGGSTA2 Bits 48-55 of PTE, defined
differently depending on non-EDAT
or EDAT-1 format: non-EDAT
(Format 0): bits 48-52 of PTO bit
53 - ignored bit 54 - Page
protection bit bit 55 - reserved,
must be 0 EDAT (Format 1): bit
48-51 Access-Control bits bit 52
- Fetch Protection bit 53 - 0,
use non-EDAT fmt 1, use EDAT
format bit 54 - DAT protection
bit bit 55 - IEP bit
1111 .... SEGGACC X'F0' SEGGACC Access-Control bits
(EDAT-1) Bits 48-51
.... 1... SEGGFETP X'08' SEGGFETP Fetch-Protection
bit Bit 52
.... .1.. SEGGFORM X'04' SEGGFORM Format Control bit
Bit 53
.... ..1. SEGGPROT X'02' SEGGPROT Entire segment is
page protected Bit 54 Obsolete.
SEGGCHOV was never implemented.
Bit 55
.... ...1 SEGGIEP X'01' SEGGIEP
Instruction-Execution-Protection
Bit 55
0007 7 Bitstring 1 SEGGSTAT Bits 56-63 Segment Table Entry
Status
..1. .... SEGGINVL X'20' SEGGINVL Bit 58 Segment
Table Entry is invalid. In a
Format 0 STE, bits 0-52 do not
necessarily contain a valid
Page-Table Origin (PTO). In a
Format 1 STE, bits 0-43 do not
necessarily contain a valid
Segment-Frame Absolute Address
(SFAA)
...1 .... SEGGCOMN X'10' SEGGCOMN Bit 59 Common
segment bit - must be 0 in all
z/VM host STEs
.... 11.. SEGGTTBT X'0C' SEGGTTBT Bits 60-61 Table
Type bits - must be b'00' because
it's a segment table
.... ...1 SEGGNULL X'01' SEGGNULL Bit 63 Segment
cannot be allocated for virtual
storage, it is not addressable.
This bit is architected as
available for software and is
ignored by hardware. PREFIX_LEN =
3
architecture, must be zero (in
either STE format) when EDAT
enabled
Note that TMLL is used to test SEGGINVL and SEGGNULL (in a
register copy of the STE contents) at the same time. This
creates a dependency on SEGGINVL being to the left of and in
the same halfword as SEGGNULL.
00000000 SEGG SEG64
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