| |
Hex Dec Type/Val Lng Label (dup) Comments
---- ---- --------- ---- -------------- --------
0000 0 Structure PFXPG PREFIX PAGE FOR ALL HOST CPU'S
0000 0 Dbl-Word 8 PFXMACHN (64) MACHINE USAGE
0200 512 Dbl-Word 8 PFXMACCM (24) Machine communication area
02C0 704 Dbl-Word 8 PFXTIMES (8) CPU Timer Region
0300 768 Dbl-Word 8 PFXSAVES (192) Static Save Areas
0900 2304 Dbl-Word 8 PFXADCON (32) ADDRESS CONSTANT
0A00 2560 Dbl-Word 8 PFXCONST (32) COMMON CONSTANTS
0B00 2816 Dbl-Word 8 PFXCNTRL (112) CPU Control Region
0E80 3712 Dbl-Word 8 PFXCPCRS (16) CP images of host control
registers
0F00 3840 Bitstring 256 PFXPATCH FE Patch Area, 32D = 64F = 128H
MACHINE USAGE - COVERED BY LOW ADDRESS PROTECT
0000 0 Dbl-Word 8 PFXILPSW IPL START PSW, RESTART NEW PSW
0008 8 Dbl-Word 8 PFXRSTOP (0) RESTART OLD PSW
0008 8 Dbl-Word 8 PFXICCW1 IPL CCW, RESTART OLD PSW
0010 16 Dbl-Word 8 PFXICCW2 IPL CCW
0018 24 Dbl-Word 8 PFXEXTOP EXTERNAL OLD PSW
0020 32 Dbl-Word 8 PFXSVCOP SVC OLD PSW
0028 40 Dbl-Word 8 PFXPRGOP PROGRAM OLD PSW
0030 48 Dbl-Word 8 PFXMCHOP MACHINE CHECK OLD PSW
0038 56 Dbl-Word 8 PFXIOOP INPUT/OUTPUT OLD PSW
0040 64 Signed 4 * RESERVED FOR FUTURE HARDWARE USE
0044 68 Signed 4 * RESERVED FOR FUTURE HARDWARE USE
0048 72 Signed 4 * RESERVED FOR FUTURE HARDWARE USE
004C 76 Signed 4 * RESERVED FOR FUTURE HARDWARE USE
0050 80 Signed 4 * RESERVED FOR FUTURE HARDWARE USE
0054 84 Signed 4 * RESERVED FOR FUTURE HARDWARE USE
0058 88 Dbl-Word 8 PFXEXTNP EXTERNAL NEW PSW
0060 96 Dbl-Word 8 PFXSVCNP SVC NEW PSW
0068 104 Dbl-Word 8 PFXPRGNP PROGRAM NEW PSW
0070 112 Dbl-Word 8 PFXMCHNP MACHINE CHECK NEW PSW
0078 120 Dbl-Word 8 PFXIONP INPUT/OUTPUT NEW PSW
0080 128 Dbl-Word 8 PFXCPULG (0) CPU AND STORAGE LOGOUT AREA
0080 128 Signed 4 PFXEXTPM (0) External interruption parameter
.... .... EXTIMIEA X'80000000' EXTIMIEA Invalid
entry address
.... .... EXTIMISE X'40000000' EXTIMISE Incorrect
SDBT entry
.... .... EXTIMPRA X'20000000' EXTIMPRA Program
request alert
PFXEXTPM EXTIMSAC X'00800000' EXTIMSAC Sampling
authorization change
PFXEXTPM EXTIMLSD X'00400000' EXTIMLSD Loss of
sample data
PFXEXTPM EXTITSC X'00020000' EXTITSC Timing-status
change
PFXEXTPM EXTILAC X'00010000' EXTILAC
Link-availability change
PFXEXTPM EXTITPC X'00008000' EXTITPC
Time-control-parameter change
PFXEXTPM EXTIMLMT X'00008000' EXTIMLMT
Loss-of-MT-counter-data
1... .... EXTIMCAC X'00000080' EXTIMCAC Counter
authorization change
.1.. .... EXTIMLCD X'00000040' EXTIMLCD Loss of
counter data
0080 128 Signed 4 PFXEXTDB PROCESSOR CONTROLLER DATA BLOCK
ADDRESS FOR SERVICE SIGNAL
INTERRUPT
0084 132 Signed 4 PFXEXTCF (0) EXTERNAL INTERRUPT CODE FIELDS
0084 132 Signed 2 PFXEXTCP EXTERNAL INTERRUPT CPU ADDR
0086 134 Signed 2 PFXEXTIN (0) EXTERNAL INTERRUPT CODE
0086 134 Bitstring 1 PFXEXTCL EXTERNAL INTERRUPT CLASS CODE
00000000 EXTICL00 00 EXTICL00 CLASS 00 EXTERNAL
INTERRUPTS (INTERRUPT KEY,
INTERVAL TIMER)
00000010 EXTICL10 16 EXTICL10 CLASS 10 EXTERNAL
INTERRUPTS (TIMER, COMPARATOR,
TOD SYNCH)
00000012 EXTICL12 18 EXTICL12 CLASS 12 EXTERNAL
INTERRUPTS (MULTI-CPU SIGNALS)
00000014 EXTICL14 20 EXTICL14 CLASS 14 EXTERNAL
INTERRUPTS (ETR INTERRUPTS)
00000020 EXTICL20 32 EXTICL20 Class 20 external
interrupts (Time zone transition)
00000024 EXTICL24 36 EXTICL24 CLASS 24 EXTERNAL
INTERRUPTS (SERVICE SIGNALS)
00000026 EXTICL26 38 EXTICL26 CLASS 26 EXTERNAL
INTERRUPTS (ESA/XC INTERRUPTS)
00000040 EXTICL40 64 EXTICL40 CLASS 40 EXTERNAL
INTERRUPTS (VMCF AND IUCV
COMMUNICATION)
0087 135 Bitstring 1 PFXEXTCD EXTERNAL INTERRUPT TYPE CODE
00000040 EXTIKEY 64 EXTIKEY CODE X'0040' INTERRUPT
KEY
00000080 EXTITMR 128 EXTITMR CODE X'0080' 370
INTERVAL TIMER
00000004 EXTICKC 04 EXTICKC CODE X'1004' CLOCK
COMPARATOR
00000005 EXTICPU 05 EXTICPU CODE X'1005' CPU TIMER
00000000 EXTIMALF 00 EXTIMALF CODE X'1200'
MALFUNCTION ALERT
00000001 EXTIEMGS 01 EXTIEMGS CODE X'1201'
EMERGENCY SIGNAL
00000002 EXTICALL 02 EXTICALL CODE X'1202' EXTERNAL
CALL
00000006 EXTIETR 06 EXTIETR CODE X'1406' ETR
INTERRUPT
00000007 EXTIMEAS 07 EXTIMEAS Code X'1407'
Measurement Alert
00000004 EXTITZCH 04 EXTITZCH CODE X'2004' Time
Zone Change
00000001 EXTISVSG 01 EXTISVSG CODE X'2401' SERVICE
SIGNAL
00000002 EXTIPVM 02 EXTIPVM CODE X'2402' PVM
LOGICAL DEVICE
00000003 EXTIXC 03 EXTIXC CODE X'2603' ESA/XC and
other VM external interrupts
00000000 EXTIIUCV 00 EXTIIUCV CODE X'4000' IUCV
INTERRUPTION
00000001 EXTIVMCF 01 EXTIVMCF CODE X'4001' VMCF
INTERRUPTION
0088 136 Signed 4 PFXSVCIF (0) SVC INTERRUPT CODE FIELDS
0088 136 Signed 2 PFXSVCIL SVC INSTRUCTION LENGTH CODE
008A 138 Signed 2 PFXSVCNT (0) SVC Interrupt Code (halfword)
008A 138 Bitstring 1 * SVC Interrupt Code (1st byte)
008B 139 Bitstring 1 PFXSVCIC SVC Interrupt Code (2nd byte)
00000000 SVCABEND 00 SVCABEND SVC 00 = HOST CP
SYSTEM ABEND
00000004 SVCSABND 04 SVCSABND SVC 04 = HOST CP
SYSTEM SOFT ABEND
0000001C SVCTRAP 28 SVCTRAP SVC 28 = PROCESS DATA
TYPE TRACE (TRACE SERVICE TOOL)
00000020 SVCTRET 32 SVCTRET SVC 32 = RETURN FROM
DATA TYPE TRACE (TRACE SERVICE
TOOL) PROCESSING
00000024 SVCSDABN 36 SVCSDABN SVC 36 = Host CP
Snapdump ABEND
00000028 SVCEXIT 40 SVCEXIT SVC 40 = Dynamic CP
Exit
0000004C SVC76ERP 76 SVC76ERP SVC 76 = ERROR
RECORDING MODULE CALL
008C 140 Signed 4 PFXPRGCF (0) PROGRAM INTERRUPT CODE FIELDS
008C 140 Signed 2 PFXPRGIL PROGRAM INTERRUPT INSTRUCTION
LENGTH CODE
00000002 TXHAILC 2 TXHAILC Default ILC used when
propagating an interruption to
the guest arising from a host
interruption during a guest
transaction.
008E 142 Signed 2 PFXPRGIN (0) PROGRAM INTERRUPT CODE, HALFWORD
008E 142 Bitstring 1 PFXPRGEE Exception extension code
008F 143 Bitstring 1 PFXPRGIC PROGRAM INTERRUPT CODE
00000136 PRGIADCP X'0136' PRGIADCP Addressing
capability
00000400 PRGITXHA X'0400' PRGITXHA Host
interrupting guest TX
00000200 PRGITRXA X'0200' PRGITRXA Transaction
aborted by PRG intrpt
00000600 PRGITXMD PRGITXHA+PRGITRXA PRGITXMD TX
modifiers combined
00000680 PRGIHMOD PRGITXHA+PRGITRXA+PRGIPER
PRGIHMOD Prg intrpt modifiers
used in host interruption
handling
0000F97F PRGICHMD X'FFFF'-PRGIHMOD PRGICHMD Mask
used for clearing host
interruption modifiers
0090 144 Signed 4 PFXTRXAD (0) Translation-Exception Ident. ESA
(Fault address/related info) ESA
- see PFXGTRAD for z/Arch ESA
0090 144 Bitstring 3 * ESA
0093 147 Bitstring 1 PFXTRXA3 FLAGS FOR TRANSLATION SPACE ID
ESA
.... .... PRGXPRIM X'00' PRGXPRIM Primary space
.... ...1 PRGXAR X'01' PRGXAR
Access-register-specified space
.... ..1. PRGXSEC X'02' PRGXSEC Secondary space
.... ..11 PRGXHOME X'03' PRGXHOME Home space zArch
Translation-Exception
Identification byte 7 bit
definitions for protection codes
for ESOP-2
1... 11.. PRGESOP2M X'8C' PRGESOP2M ESOP-2 Protection
Code Mask
.... .1.. PRGESOP2D X'04' PRGESOP2D ESOP-2 Protection
Code DATP
.... 1... PRGESOP2K X'08' PRGESOP2K ESOP-2 Protection
Code KCP
.... 11.. PRGESOP2A X'0C' PRGESOP2A ESOP-2 Protection
Code ALCP
1... .... PRGESOP2L X'80' PRGESOP2L ESOP-2 Protection
Code LAP
1... .1.. PRGESOP2I X'84' PRGESOP2I ESOP-2 Protection
Code IEP Other bits defined in
low byte of TEID:
.... .1.. PRGXMVPG X'04' PRGXMVPG Exception occurred
on MVPG instructn Data exception
codes
1111 111. PRGDXCVR X'FE' PRGDXCVR Vector-register
data exception
.... ..1. PRGDXBFP X'02' PRGDXBFP BFP-instruction
data exception
.... ...1 PRGDXAFP X'01' PRGDXAFP AFP-register data
exception
0090 144 Signed 4 PFXFPARM (0) Data exception information
0090 144 Bitstring 3 *
0093 147 Bitstring 1 PFXDXCOD Data exception code
0090 144 Signed 4 PFXVPARM (0) Vector exception information
0090 144 Bitstring 3 *
0093 147 Bitstring 1 PFXVXCOD Vector exception code
0094 148 Signed 2 PFXMNCLS MONITOR CLASS
0096 150 Signed 2 PFXPERCD PROGRAM EVENT RECORDER (PER) CODE
0098 152 Signed 4 PFXPERAD PER Address ESA - see PFXGPERA
for z/Arch ESA
009C 156 Signed 4 PFXMNCOD Monitor interrupt code ESA - see
PFXGMNCD for z/Arch ESA
0098 152 Dbl-Word 8 PFXGPERA (0) PER Address for z/Architecture
mode
0098 152 Signed 4 PFXGPERL Left Half PER address
009C 156 Signed 4 PFXGPERR Right Half PER address
00A0 160 Bitstring 1 PFXXCPAR EXCEPTION ACCESS IDENTIFICATION
..1. .... PRGXCPRI X'20' PRGXCPRI Primary-tran
problem (not Access Register
related)
...1 .... PRGXCSEC X'10' PRGXCSEC Secondary-tran
problem (not Access Register
related)
.... 1111 PRGXCREG X'0F' PRGXCREG Access-register
number
00A1 161 Bitstring 1 PFXPERAR PER ACCESS IDENTIFICATION
00A2 162 Bitstring 1 PFXOPRID Operand access identification
00A3 163 Bitstring 1 PFXARCHM Architectural Mode ID
.... ...1 PFXAINME X'01' PFXAINME Bit 7 on indicates
CP is currently executing in
z/Architecture mode. When off CP
is currently in ESA/390 mode.
00A4 164 Signed 4 * RESERVED FOR FUTURE HARDWARE USE
00A8 168 Dbl-Word 8 PFXGTRAD Translation-Exception Ident.
z/Arch - see PFXTRXAD for ESA/390
00B0 176 Dbl-Word 8 PFXGMNCD (0) Monitor interrupt code
00B0 176 Signed 4 PFXGMNCL Monitor interrupt code left
00B4 180 Signed 4 PFXGMNCR Monitor interrupt code right -
see PFXMNCOD for ESA/390
00B4 180 Bitstring 2 * Zero
00B6 182 Bitstring 1 PFXGMNAC Actual class
00B7 183 Bitstring 1 PFXGMNAR Actual record
00A8 168 Signed 4 * RESERVED FOR FUTURE HW USE ESA
00AC 172 Signed 4 * RESERVED FOR FUTURE HW USE ESA
00B0 176 Signed 4 * RESERVED FOR FUTURE HW USE ESA
00B4 180 Signed 4 * RESERVED FOR FUTURE HW USE ESA
00B8 184 Signed 4 PFXIOSID (0) SUBCHANNEL IDENTIFICATION
00B8 184 Signed 2 PFXIOINT I/O INTERRUPT CONSTANT 0001
00BA 186 Signed 2 PFXIORNM I/O INTERRUPT SUBCHANNEL NUMBER
00B8 184 Signed 4 PFXIOICA (0) I/O Int Code Word 0 - I/O
Adapters
00B8 184 Bitstring 1 PFXAISM Adapter-Interruption Source
Mask-AISM
1... .... PFXQDIOA X'80' PFXQDIOA QDIO Adapter
Interrupt
.1.. .... PFXPCIA X'40' PFXPCIA PCI Function
Interrupt
00B9 185 Bitstring 1 * Reserved for IBM future use
00BA 186 Bitstring 1 * Reserved for IBM future use
00BB 187 Bitstring 1 PFXADPFG Adapter Flags
.... ..1. PFXEBIT X'02' PFXEBIT Host Error
Condition
.... ...1 PFXHBIT X'01' PFXHBIT Host Forwarding
Request
00BC 188 Signed 4 PFXINPRM I/O INTERRUPT PARAMETER
00C0 192 Signed 4 PFXINTID (0) INTERRUPTION ID WORD:
00C0 192 Bitstring 1 PFXINISC FIRST BYTE - THE ISC
00000080 PFXIOADP X'80' PFXIOADP Adapter Interrupt
000000B0 PFXINIFI X'30'+PFXIOADP PFXINIFI Use
Alternate I/O FLIH
00C1 193 Bitstring 1 * Reserved for IBM future use
00C2 194 Bitstring 1 PFXSCHTP Subchannel type
00000000 PFXSCHT0 X'00' PFXSCHT0 Type 0 subchannel
00000070 PFXSCHTM X'70' PFXSCHTM Mask for location
of subchannel type bits within
this byte.
00C3 195 Bitstring 1 * Reserved for IBM future use
00C4 196 Signed 4 * RESERVED FOR FUTURE HARDWARE USE
00C8 200 Signed 4 PFXSTFL (0) STFL facilities list
00C8 200 Bitstring 1 PFXSTFL0 Byte 0, Bits 0-7
1... .... STFL0N3A X'80' STFL0N3A "N3" instructions
available
.1.. .... STFL0MEA X'40' STFL0MEA zArch available
..1. .... STFL0MEE X'20' STFL0MEE zArch enabled
...1 .... STFL0IDT X'10' STFL0IDT IDTE is installed
.... 1... STFL0ICS X'08' STFL0ICS IDTE performs the
Invalidation-and- Clearing
operation selectively when STE(s)
are invalidated. IDTE also
performs the Clearing-by-ASCE
function selectively. In both
cases, "selectively" means the
TLB purging is limited to those
specific entries required by
architecture. If this bit is off,
IDTE simply purges all TLBs. If
this bit is on, STFL0IDT is also
on.
.... .1.. STFL0ICR X'04' STFL0ICR IDTE performs the
Invalidation-and- Clearing
operation selectively when RTE(s)
are invalidated. "Selectively"
means the TLB purging is limited
to those specific entries
required by architecture. If this
bit is off, IDTE
Invalidation-and-Clearing of
RTE(s) simply purges all TLBs. If
this bit is on, STFL0IDT and
STFL0ICS are also on.
.... ..1. STFL0ALR X'02' STFL0ALR ASN-and-LX-reuse
facility installed
.... ...1 STFL0FLE X'01' STFL0FLE STFLE facility
installed Absolute bit position
definitiions for byte 0 for use
with HCPARDSF
00C9 201 Bitstring 1 PFXSTFL1 Byte 1, bits 8-15
1... .... STFLEDAT X'80' STFLEDAT Enhanced-DAT
facility (z/Arch)
.1.. .... STFLSRS X'40' STFLSRS
Sense-running-status facility
..1. .... STFLSSKE X'20' STFLSSKE Conditional-SSKE
(z/Arch)
...1 .... STFLCTOP X'10' STFLCTOP
Configuration-Topology (z/Arch)
.... 1... STFLIBM4 X'08' STFLIBM4 Assigned to IBM
Internal Use
.... .1.. STFLIPTR X'04' STFLIPTR IPTE-Range
(z/Arch)
.... ..1. STFLNQKS X'02' STFLNQKS
Non-Quiescing-Key-Setting
(z/Arch)
.... ...1 STFLIBM1 X'01' STFLIBM1 Assigned to IBM
Internal Use. Absolute bit
position definitiions for byte 1
for use with HCPARDSF
00CA 202 Bitstring 1 PFXSTFL2 Byte 2, bits 16-23
1... .... STFLETF2 X'80' STFLETF2 Extended
Translation Facility 2
.1.. .... STFLCCA X'40' STFLCCA CPU Crypto Assist
installed
..1. .... STFLLDF X'20' STFLLDF Long Displacement
Facility available
...1 .... STFLHPO X'10' STFLHPO LDF High
Performance Option installed
.... 1... STFLHFPM X'08' STFLHFPM
HFP-Mult-Add/Subtract facility
.... .1.. STFLEXTI X'04' STFLEXTI Extended-Immediate
facility installed
.... ..1. STFLETF3 X'02' STFLETF3 Extended-Trans
Facility 3 installed
.... ...1 STFLHFPU X'01' STFLHFPU
HFP-Unnormalized-extension
facility Absolute bit position
definitiions for byte 2 for use
with HCPARDSF
00CB 203 Bitstring 1 PFXSTFL3 Byte 3, bits 24-31
1... .... STFLE2EN X'80' STFLE2EN ETF2-Enhancement
Facility installed
.1.. .... STFLSTCF X'40' STFLSTCF Store-Clock-Fast
Facility
..1. .... STFLPARS X'20' STFLPARS
Parsing-enhancement Facility
installed
...1 .... STFLMVCS X'10' STFLMVCS
Move-with-optional-specifications
.... 1... STFLPTFF X'08' STFLPTFF TOD-clock steering
facility installed
.... ..1. STFLE3EN X'02' STFLE3EN ETF3-Enhancement
Facility installed
.... ...1 STFLECTG X'01' STFLECTG Extract-CPU-Time
Facility installed Absolute bit
position definitiions for byte 3
for use with HCPARDSF
00CC 204 Signed 4 * RESERVED FOR FUTURE HARDWARE USE
00D0 208 Signed 4 * RESERVED FOR FUTURE HARDWARE USE
00D4 212 Signed 4 PFXFPXSA Extended-Save-Area Address ESA
00D4 212 Signed 4 * Reserved for IBM hardware use
00D8 216 Dbl-Word 8 PFXMCPUT Machine check CPU Timer logout
ESA - see PF2CPTLG for z/Arch ESA
00E0 224 Dbl-Word 8 PFXMCKCP Machine check TOD Comp. logout
ESA - see PF2CKCLG for z/Arch ESA
00E8 232 Dbl-Word 8 PFXMCHIN MACHINE CHECK INTERRUPT CODE
00F0 240 Signed 4 * RESERVED FOR FUTURE HARDWARE USE
00F4 244 Signed 4 PFXMCHDC MACHINE CHECK EXTERNAL-DAMAGE
CODE
00F8 248 Signed 4 PFXMCFSA Machine check failing storage ESA
address ESA - see PFXGMCFS for
z/Arch ESA
00FC 252 Signed 4 PFXMCHRD Machine-dependent region code ESA
- no equivalent for z/Arch ESA
00F8 248 Dbl-Word 8 PFXGMCFS Machine check failing storage
address
0100 256 Bitstring 16 PFXFXLOG MACHINE DEPENDENT FIXED LOGOUT
AREA
...1 .... PFXFXLEN L'PFXFXLOG PFXFXLEN LENGTH OF
FIXED LOGOUT AREA.
0110 272 Dbl-Word 8 PFXBEAR Breaking-Event Address EASME
0118 280 Bitstring 8 * RESERVED FOR FUTURE HARDWARE USE
0120 288 Signed 4 PFXARLG (16) Access Register Logout Area ESA
0160 352 Dbl-Word 8 PFXFPRLG (4) FLOATING POINT REG LOGOUT AREA
ESA
0180 384 Signed 4 PFXGPRLG (16) GENERAL REGISTER LOGOUT AREA ESA
01C0 448 Signed 4 PFXCRLG (16) CONTROL REGISTER LOGOUT AREA ESA
00000040 PFXCRLGL (L'PFXCRLG*16) LENGTH OF CR
LOGOUT AREA ESA
0120 288 Bitstring 16 PFXGRSTO Restart Old PSW
0130 304 Bitstring 16 PFXGEXTO External Old PSW
0140 320 Bitstring 16 PFXGSVCO Supervisor-Call Old PSW
0150 336 Bitstring 16 PFXGPRGO Program Old PSW
0160 352 Bitstring 16 PFXGMCHO Machine-Check Old PSW
0170 368 Bitstring 16 PFXGIOO Input/Output Old PSW
0180 384 Dbl-Word 8 * (4) Reserved for hardware use
01A0 416 Bitstring 16 PFXGRSTN Restart New PSW
01B0 432 Bitstring 16 PFXGEXTN External New PSW
01C0 448 Bitstring 16 PFXGSVCN Supervisor-Call New PSW
01D0 464 Bitstring 16 PFXGPRGN Program New PSW
01E0 480 Bitstring 16 PFXGMCHN Machine-Check New PSW
01F0 496 Bitstring 16 PFXGION Input/Output New PSW
00000200 PFXLAPND * END OF AREA COVERED BY LOW
ADDRESS PROTECTION
0000 0 Bitstring 1 PFXILPO0 ILP PSW BYTE 0
.1.. .... PSWPERA X'40' PSWPERA PROGRAM EVENT
RECORDING ACTIVE
.... .1.. PSWTRAN X'04' PSWTRAN ADDRESS TRANSLATE
MODE ACTIVE
.... ..1. PSWIOSM X'02' PSWIOSM I/O INTERRUPTION
SUMMARY MASK
.... ...1 PSWEXSM X'01' PSWEXSM EXTERNAL INTERRUPT
SUMMARY MASK
0001 1 Bitstring 1 PFXILPO1 ILP PSW BYTE 1
1111 .... PSWKEY X'F0' PSWKEY PSW ACCESS KEY
EXTRACTION MASK
.... 1... PSWECMD X'08' PSWECMD EXTENDED CONTROL
MODE ACTIVE
.... .1.. PSWMCHK X'04' PSWMCHK MACHINE CHECK
SUMMARY MASK
.... ..1. PSWWAIT X'02' PSWWAIT PROGRAM WAIT STATE
.... ...1 PSWPROB X'01' PSWPROB PROGRAM PROBLEM
STATE
.... ...1 PSWMAPPD X'01' PSWMAPPD For BC-mode PSWs
created by the 370 Accommodation
facility, this bit being set
indicates that the PSW is really
a "mapped" PSW. See HCPPSW.
0002 2 Bitstring 1 PFXILPO2 ILP PSW BYTE 2
11.. .... PSWASMSK X'C0' PSWASMSK ADDRESS SPACE
CONTROL MASK
11.. .... PSWHMODE X'C0' PSWHMODE HOME-SPACE MODE
1... .... PSWSMODE X'80' PSWSMODE SECONDARY MODE
.1.. .... PSWAMODE X'40' PSWAMODE ACCESS-REGISTER
MODE
..11 .... PSWCOND X'30' PSWCOND PSW CONDITION CODE
..1. .... PSWCOND2 X'20' PSWCOND2 PSW CONDITION CODE
BIT FOR CC=2,3
...1 .... PSWCOND1 X'10' PSWCOND1 PSW CONDITION CODE
BIT FOR CC=1,3
.... 1111 PSWPMSK X'0F' PSWPMSK FIXO+DECO+EXUN+SIGN
PROGRAM MASK
.... 1... PSWFIXO X'08' PSWFIXO FIXED-PT OVERFLOW
INTRPT MASK
.... .1.. PSWDECO X'04' PSWDECO DECIMAL OVERFLOW
INTRPT MASK
.... ..1. PSWEXUN X'02' PSWEXUN EXPONENT UNDERFLOW
INTRPT MASK
.... ...1 PSWSIGN X'01' PSWSIGN SIGNIFICANCE
INTERRUPT MASK
.... .... PSWPMODE X'00' PSWPMODE PRIMARY-SPACE MODE
0003 3 Bitstring 1 PFXILPO3 ILP PSW BYTE 3
0004 4 Signed 4 PFXILPOI (0) ILP PSW INSTRUCTION COUNTER
0004 4 Bitstring 1 PFXILPO4 ILP PSW BYTE 4
1... .... PSW31BT X'80' PSW31BT 31-BIT LOGICAL
ADDRESSING MODE
1... .... PSWBA PSW31BT PSWBA Basic Addressing
Mode
.111 1111 PSWHIADR X'7F' PSWHIADR INSTRUCTION
COUNTER BITS 1-7 - MUST BE ZERO
IN 24-BIT MODE.
.... .... PSW31AMF X'80000000' PSW31AMF ADDRESS MODE
FULLWORD MASK - CORRESPONDS TO
PSW31BT
0005 5 Bitstring 1 * (3) ILP PSW BYTES 5-7
0010 16 Bitstring 1 PFXSGPND SIGP RESTART FUNCTION COMPLETION
FLAG
000000FF PFXSGPGD 255 PFXSGPGD SUCCESSFUL
COMPLETION
000000EE PFXSGPNG 238 PFXSGPNG NOT SUCCESSFUL
COMPLETION
0011 17 Bitstring 7 PFXCC2B1 (0) BYTES 1-7 OF PFXICCW2
0011 17 Bitstring 1 * (5) RESERVED FOR FUTURE USE
0016 22 Bitstring 2 PFXSGPCP SIGP RESTART FUNCTION WORK AREA
0018 24 Bitstring 1 PFXEXTO0 EXT OLD PSW BYTE 0
.1.. .... PSWPERA X'40' PSWPERA PROGRAM EVENT
RECORDING ACTIVE
.... .1.. PSWTRAN X'04' PSWTRAN ADDRESS TRANSLATE
MODE ACTIVE
.... ..1. PSWIOSM X'02' PSWIOSM I/O INTERRUPTION
SUMMARY MASK
.... ...1 PSWEXSM X'01' PSWEXSM EXTERNAL INTERRUPT
SUMMARY MASK
0019 25 Bitstring 1 PFXEXTO1 EXT OLD PSW BYTE 1
1111 .... PSWKEY X'F0' PSWKEY PSW ACCESS KEY
EXTRACTION MASK
.... 1... PSWECMD X'08' PSWECMD EXTENDED CONTROL
MODE ACTIVE
.... .1.. PSWMCHK X'04' PSWMCHK MACHINE CHECK
SUMMARY MASK
.... ..1. PSWWAIT X'02' PSWWAIT PROGRAM WAIT STATE
.... ...1 PSWPROB X'01' PSWPROB PROGRAM PROBLEM
STATE
.... ...1 PSWMAPPD X'01' PSWMAPPD For BC-mode PSWs
created by the 370 Accommodation
facility, this bit being set
indicates that the PSW is really
a "mapped" PSW. See HCPPSW.
001A 26 Bitstring 1 PFXEXTO2 EXT OLD PSW BYTE 2
11.. .... PSWASMSK X'C0' PSWASMSK ADDRESS SPACE
CONTROL MASK
11.. .... PSWHMODE X'C0' PSWHMODE HOME-SPACE MODE
1... .... PSWSMODE X'80' PSWSMODE SECONDARY MODE
.1.. .... PSWAMODE X'40' PSWAMODE ACCESS-REGISTER
MODE
..11 .... PSWCOND X'30' PSWCOND PSW CONDITION CODE
..1. .... PSWCOND2 X'20' PSWCOND2 PSW CONDITION CODE
BIT FOR CC=2,3
...1 .... PSWCOND1 X'10' PSWCOND1 PSW CONDITION CODE
BIT FOR CC=1,3
.... 1111 PSWPMSK X'0F' PSWPMSK FIXO+DECO+EXUN+SIGN
PROGRAM MASK
.... 1... PSWFIXO X'08' PSWFIXO FIXED-PT OVERFLOW
INTRPT MASK
.... .1.. PSWDECO X'04' PSWDECO DECIMAL OVERFLOW
INTRPT MASK
.... ..1. PSWEXUN X'02' PSWEXUN EXPONENT UNDERFLOW
INTRPT MASK
.... ...1 PSWSIGN X'01' PSWSIGN SIGNIFICANCE
INTERRUPT MASK
.... .... PSWPMODE X'00' PSWPMODE PRIMARY-SPACE MODE
001B 27 Bitstring 1 PFXEXTO3 EXT OLD PSW BYTE 3
001C 28 Signed 4 PFXEXTOI (0) EXT OLD PSW INSTRUCTION COUNTER
001C 28 Bitstring 1 PFXEXTO4 EXT OLD PSW BYTE 4
1... .... PSW31BT X'80' PSW31BT 31-BIT LOGICAL
ADDRESSING MODE
1... .... PSWBA PSW31BT PSWBA Basic Addressing
Mode
.111 1111 PSWHIADR X'7F' PSWHIADR INSTRUCTION
COUNTER BITS 1-7 - MUST BE ZERO
IN 24-BIT MODE.
.... .... PSW31AMF X'80000000' PSW31AMF ADDRESS MODE
FULLWORD MASK - CORRESPONDS TO
PSW31BT
001D 29 Bitstring 1 * (3) EXT OLD PSW BYTES 5-7
0020 32 Bitstring 1 PFXSVCO0 SVC OLD PSW BYTE 0
.1.. .... PSWPERA X'40' PSWPERA PROGRAM EVENT
RECORDING ACTIVE
.... .1.. PSWTRAN X'04' PSWTRAN ADDRESS TRANSLATE
MODE ACTIVE
.... ..1. PSWIOSM X'02' PSWIOSM I/O INTERRUPTION
SUMMARY MASK
.... ...1 PSWEXSM X'01' PSWEXSM EXTERNAL INTERRUPT
SUMMARY MASK
0021 33 Bitstring 1 PFXSVCO1 SVC OLD PSW BYTE 1
1111 .... PSWKEY X'F0' PSWKEY PSW ACCESS KEY
EXTRACTION MASK
.... 1... PSWECMD X'08' PSWECMD EXTENDED CONTROL
MODE ACTIVE
.... .1.. PSWMCHK X'04' PSWMCHK MACHINE CHECK
SUMMARY MASK
.... ..1. PSWWAIT X'02' PSWWAIT PROGRAM WAIT STATE
.... ...1 PSWPROB X'01' PSWPROB PROGRAM PROBLEM
STATE
.... ...1 PSWMAPPD X'01' PSWMAPPD For BC-mode PSWs
created by the 370 Accommodation
facility, this bit being set
indicates that the PSW is really
a "mapped" PSW. See HCPPSW.
0022 34 Bitstring 1 PFXSVCO2 SVC OLD PSW BYTE 2
11.. .... PSWASMSK X'C0' PSWASMSK ADDRESS SPACE
CONTROL MASK
11.. .... PSWHMODE X'C0' PSWHMODE HOME-SPACE MODE
1... .... PSWSMODE X'80' PSWSMODE SECONDARY MODE
.1.. .... PSWAMODE X'40' PSWAMODE ACCESS-REGISTER
MODE
..11 .... PSWCOND X'30' PSWCOND PSW CONDITION CODE
..1. .... PSWCOND2 X'20' PSWCOND2 PSW CONDITION CODE
BIT FOR CC=2,3
...1 .... PSWCOND1 X'10' PSWCOND1 PSW CONDITION CODE
BIT FOR CC=1,3
.... 1111 PSWPMSK X'0F' PSWPMSK FIXO+DECO+EXUN+SIGN
PROGRAM MASK
.... 1... PSWFIXO X'08' PSWFIXO FIXED-PT OVERFLOW
INTRPT MASK
.... .1.. PSWDECO X'04' PSWDECO DECIMAL OVERFLOW
INTRPT MASK
.... ..1. PSWEXUN X'02' PSWEXUN EXPONENT UNDERFLOW
INTRPT MASK
.... ...1 PSWSIGN X'01' PSWSIGN SIGNIFICANCE
INTERRUPT MASK
.... .... PSWPMODE X'00' PSWPMODE PRIMARY-SPACE MODE
0023 35 Bitstring 1 PFXSVCO3 SVC OLD PSW BYTE 3
0024 36 Signed 4 PFXSVCOI (0) SVC OLD PSW INSTRUCTION COUNTER
0024 36 Bitstring 1 PFXSVCO4 SVC OLD PSW BYTE 4
1... .... PSW31BT X'80' PSW31BT 31-BIT LOGICAL
ADDRESSING MODE
1... .... PSWBA PSW31BT PSWBA Basic Addressing
Mode
.111 1111 PSWHIADR X'7F' PSWHIADR INSTRUCTION
COUNTER BITS 1-7 - MUST BE ZERO
IN 24-BIT MODE.
.... .... PSW31AMF X'80000000' PSW31AMF ADDRESS MODE
FULLWORD MASK - CORRESPONDS TO
PSW31BT
0025 37 Bitstring 1 * (3) SVC OLD PSW BYTES 5-7
0028 40 Bitstring 1 PFXPRGO0 PRG OLD PSW BYTE 0
.1.. .... PSWPERA X'40' PSWPERA PROGRAM EVENT
RECORDING ACTIVE
.... .1.. PSWTRAN X'04' PSWTRAN ADDRESS TRANSLATE
MODE ACTIVE
.... ..1. PSWIOSM X'02' PSWIOSM I/O INTERRUPTION
SUMMARY MASK
.... ...1 PSWEXSM X'01' PSWEXSM EXTERNAL INTERRUPT
SUMMARY MASK
0029 41 Bitstring 1 PFXPRGO1 PRG OLD PSW BYTE 1
1111 .... PSWKEY X'F0' PSWKEY PSW ACCESS KEY
EXTRACTION MASK
.... 1... PSWECMD X'08' PSWECMD EXTENDED CONTROL
MODE ACTIVE
.... .1.. PSWMCHK X'04' PSWMCHK MACHINE CHECK
SUMMARY MASK
.... ..1. PSWWAIT X'02' PSWWAIT PROGRAM WAIT STATE
.... ...1 PSWPROB X'01' PSWPROB PROGRAM PROBLEM
STATE
.... ...1 PSWMAPPD X'01' PSWMAPPD For BC-mode PSWs
created by the 370 Accommodation
facility, this bit being set
indicates that the PSW is really
a "mapped" PSW. See HCPPSW.
002A 42 Bitstring 1 PFXPRGO2 PRG OLD PSW BYTE 2
11.. .... PSWASMSK X'C0' PSWASMSK ADDRESS SPACE
CONTROL MASK
11.. .... PSWHMODE X'C0' PSWHMODE HOME-SPACE MODE
1... .... PSWSMODE X'80' PSWSMODE SECONDARY MODE
.1.. .... PSWAMODE X'40' PSWAMODE ACCESS-REGISTER
MODE
..11 .... PSWCOND X'30' PSWCOND PSW CONDITION CODE
..1. .... PSWCOND2 X'20' PSWCOND2 PSW CONDITION CODE
BIT FOR CC=2,3
...1 .... PSWCOND1 X'10' PSWCOND1 PSW CONDITION CODE
BIT FOR CC=1,3
.... 1111 PSWPMSK X'0F' PSWPMSK FIXO+DECO+EXUN+SIGN
PROGRAM MASK
.... 1... PSWFIXO X'08' PSWFIXO FIXED-PT OVERFLOW
INTRPT MASK
.... .1.. PSWDECO X'04' PSWDECO DECIMAL OVERFLOW
INTRPT MASK
.... ..1. PSWEXUN X'02' PSWEXUN EXPONENT UNDERFLOW
INTRPT MASK
.... ...1 PSWSIGN X'01' PSWSIGN SIGNIFICANCE
INTERRUPT MASK
.... .... PSWPMODE X'00' PSWPMODE PRIMARY-SPACE MODE
002B 43 Bitstring 1 PFXPRGO3 PRG OLD PSW BYTE 3
002C 44 Signed 4 PFXPRGOI (0) PRG OLD PSW INSTRUCTION COUNTER
002C 44 Bitstring 1 PFXPRGO4 PRG OLD PSW BYTE 4
1... .... PSW31BT X'80' PSW31BT 31-BIT LOGICAL
ADDRESSING MODE
1... .... PSWBA PSW31BT PSWBA Basic Addressing
Mode
.111 1111 PSWHIADR X'7F' PSWHIADR INSTRUCTION
COUNTER BITS 1-7 - MUST BE ZERO
IN 24-BIT MODE.
.... .... PSW31AMF X'80000000' PSW31AMF ADDRESS MODE
FULLWORD MASK - CORRESPONDS TO
PSW31BT
002D 45 Bitstring 1 * (3) PRG OLD PSW BYTES 5-7
0030 48 Bitstring 1 PFXMCHO0 MCH OLD PSW BYTE 0
.1.. .... PSWPERA X'40' PSWPERA PROGRAM EVENT
RECORDING ACTIVE
.... .1.. PSWTRAN X'04' PSWTRAN ADDRESS TRANSLATE
MODE ACTIVE
.... ..1. PSWIOSM X'02' PSWIOSM I/O INTERRUPTION
SUMMARY MASK
.... ...1 PSWEXSM X'01' PSWEXSM EXTERNAL INTERRUPT
SUMMARY MASK
0031 49 Bitstring 1 PFXMCHO1 MCH OLD PSW BYTE 1
1111 .... PSWKEY X'F0' PSWKEY PSW ACCESS KEY
EXTRACTION MASK
.... 1... PSWECMD X'08' PSWECMD EXTENDED CONTROL
MODE ACTIVE
.... .1.. PSWMCHK X'04' PSWMCHK MACHINE CHECK
SUMMARY MASK
.... ..1. PSWWAIT X'02' PSWWAIT PROGRAM WAIT STATE
.... ...1 PSWPROB X'01' PSWPROB PROGRAM PROBLEM
STATE
.... ...1 PSWMAPPD X'01' PSWMAPPD For BC-mode PSWs
created by the 370 Accommodation
facility, this bit being set
indicates that the PSW is really
a "mapped" PSW. See HCPPSW.
0032 50 Bitstring 1 PFXMCHO2 MCH OLD PSW BYTE 2
11.. .... PSWASMSK X'C0' PSWASMSK ADDRESS SPACE
CONTROL MASK
11.. .... PSWHMODE X'C0' PSWHMODE HOME-SPACE MODE
1... .... PSWSMODE X'80' PSWSMODE SECONDARY MODE
.1.. .... PSWAMODE X'40' PSWAMODE ACCESS-REGISTER
MODE
..11 .... PSWCOND X'30' PSWCOND PSW CONDITION CODE
..1. .... PSWCOND2 X'20' PSWCOND2 PSW CONDITION CODE
BIT FOR CC=2,3
...1 .... PSWCOND1 X'10' PSWCOND1 PSW CONDITION CODE
BIT FOR CC=1,3
.... 1111 PSWPMSK X'0F' PSWPMSK FIXO+DECO+EXUN+SIGN
PROGRAM MASK
.... 1... PSWFIXO X'08' PSWFIXO FIXED-PT OVERFLOW
INTRPT MASK
.... .1.. PSWDECO X'04' PSWDECO DECIMAL OVERFLOW
INTRPT MASK
.... ..1. PSWEXUN X'02' PSWEXUN EXPONENT UNDERFLOW
INTRPT MASK
.... ...1 PSWSIGN X'01' PSWSIGN SIGNIFICANCE
INTERRUPT MASK
.... .... PSWPMODE X'00' PSWPMODE PRIMARY-SPACE MODE
0033 51 Bitstring 1 PFXMCHO3 MCH OLD PSW BYTE 3
0034 52 Signed 4 PFXMCHOI (0) MCH OLD PSW INSTRUCTION COUNTER
0034 52 Bitstring 1 PFXMCHO4 MCH OLD PSW BYTE 4
1... .... PSW31BT X'80' PSW31BT 31-BIT LOGICAL
ADDRESSING MODE
1... .... PSWBA PSW31BT PSWBA Basic Addressing
Mode
.111 1111 PSWHIADR X'7F' PSWHIADR INSTRUCTION
COUNTER BITS 1-7 - MUST BE ZERO
IN 24-BIT MODE.
.... .... PSW31AMF X'80000000' PSW31AMF ADDRESS MODE
FULLWORD MASK - CORRESPONDS TO
PSW31BT
0035 53 Bitstring 1 * (3) MCH OLD PSW BYTES 5-7
0038 56 Bitstring 1 PFXIOPO0 I/O OLD PSW BYTE 0
.1.. .... PSWPERA X'40' PSWPERA PROGRAM EVENT
RECORDING ACTIVE
.... .1.. PSWTRAN X'04' PSWTRAN ADDRESS TRANSLATE
MODE ACTIVE
.... ..1. PSWIOSM X'02' PSWIOSM I/O INTERRUPTION
SUMMARY MASK
.... ...1 PSWEXSM X'01' PSWEXSM EXTERNAL INTERRUPT
SUMMARY MASK
0039 57 Bitstring 1 PFXIOPO1 I/O OLD PSW BYTE 1
1111 .... PSWKEY X'F0' PSWKEY PSW ACCESS KEY
EXTRACTION MASK
.... 1... PSWECMD X'08' PSWECMD EXTENDED CONTROL
MODE ACTIVE
.... .1.. PSWMCHK X'04' PSWMCHK MACHINE CHECK
SUMMARY MASK
.... ..1. PSWWAIT X'02' PSWWAIT PROGRAM WAIT STATE
.... ...1 PSWPROB X'01' PSWPROB PROGRAM PROBLEM
STATE
.... ...1 PSWMAPPD X'01' PSWMAPPD For BC-mode PSWs
created by the 370 Accommodation
facility, this bit being set
indicates that the PSW is really
a "mapped" PSW. See HCPPSW.
003A 58 Bitstring 1 PFXIOPO2 I/O OLD PSW BYTE 2
11.. .... PSWASMSK X'C0' PSWASMSK ADDRESS SPACE
CONTROL MASK
11.. .... PSWHMODE X'C0' PSWHMODE HOME-SPACE MODE
1... .... PSWSMODE X'80' PSWSMODE SECONDARY MODE
.1.. .... PSWAMODE X'40' PSWAMODE ACCESS-REGISTER
MODE
..11 .... PSWCOND X'30' PSWCOND PSW CONDITION CODE
..1. .... PSWCOND2 X'20' PSWCOND2 PSW CONDITION CODE
BIT FOR CC=2,3
...1 .... PSWCOND1 X'10' PSWCOND1 PSW CONDITION CODE
BIT FOR CC=1,3
.... 1111 PSWPMSK X'0F' PSWPMSK FIXO+DECO+EXUN+SIGN
PROGRAM MASK
.... 1... PSWFIXO X'08' PSWFIXO FIXED-PT OVERFLOW
INTRPT MASK
.... .1.. PSWDECO X'04' PSWDECO DECIMAL OVERFLOW
INTRPT MASK
.... ..1. PSWEXUN X'02' PSWEXUN EXPONENT UNDERFLOW
INTRPT MASK
.... ...1 PSWSIGN X'01' PSWSIGN SIGNIFICANCE
INTERRUPT MASK
.... .... PSWPMODE X'00' PSWPMODE PRIMARY-SPACE MODE
003B 59 Bitstring 1 PFXIOPO3 I/O OLD PSW BYTE 3
003C 60 Signed 4 PFXIOPOI (0) I/O OLD PSW INSTRUCTION COUNTER
003C 60 Bitstring 1 PFXIOPO4 I/O OLD PSW BYTE 4
1... .... PSW31BT X'80' PSW31BT 31-BIT LOGICAL
ADDRESSING MODE
1... .... PSWBA PSW31BT PSWBA Basic Addressing
Mode
.111 1111 PSWHIADR X'7F' PSWHIADR INSTRUCTION
COUNTER BITS 1-7 - MUST BE ZERO
IN 24-BIT MODE.
.... .... PSW31AMF X'80000000' PSW31AMF ADDRESS MODE
FULLWORD MASK - CORRESPONDS TO
PSW31BT
003D 61 Bitstring 1 * (3) I/O OLD PSW BYTES 5-7
0058 88 Bitstring 1 PFXEXTN0 EXT NEW PSW BYTE 0
.1.. .... PSWPERA X'40' PSWPERA PROGRAM EVENT
RECORDING ACTIVE
.... .1.. PSWTRAN X'04' PSWTRAN ADDRESS TRANSLATE
MODE ACTIVE
.... ..1. PSWIOSM X'02' PSWIOSM I/O INTERRUPTION
SUMMARY MASK
.... ...1 PSWEXSM X'01' PSWEXSM EXTERNAL INTERRUPT
SUMMARY MASK
0059 89 Bitstring 1 PFXEXTN1 EXT NEW PSW BYTE 1
1111 .... PSWKEY X'F0' PSWKEY PSW ACCESS KEY
EXTRACTION MASK
.... 1... PSWECMD X'08' PSWECMD EXTENDED CONTROL
MODE ACTIVE
.... .1.. PSWMCHK X'04' PSWMCHK MACHINE CHECK
SUMMARY MASK
.... ..1. PSWWAIT X'02' PSWWAIT PROGRAM WAIT STATE
.... ...1 PSWPROB X'01' PSWPROB PROGRAM PROBLEM
STATE
.... ...1 PSWMAPPD X'01' PSWMAPPD For BC-mode PSWs
created by the 370 Accommodation
facility, this bit being set
indicates that the PSW is really
a "mapped" PSW. See HCPPSW.
005A 90 Bitstring 1 PFXEXTN2 EXT NEW PSW BYTE 2
11.. .... PSWASMSK X'C0' PSWASMSK ADDRESS SPACE
CONTROL MASK
11.. .... PSWHMODE X'C0' PSWHMODE HOME-SPACE MODE
1... .... PSWSMODE X'80' PSWSMODE SECONDARY MODE
.1.. .... PSWAMODE X'40' PSWAMODE ACCESS-REGISTER
MODE
..11 .... PSWCOND X'30' PSWCOND PSW CONDITION CODE
..1. .... PSWCOND2 X'20' PSWCOND2 PSW CONDITION CODE
BIT FOR CC=2,3
...1 .... PSWCOND1 X'10' PSWCOND1 PSW CONDITION CODE
BIT FOR CC=1,3
.... 1111 PSWPMSK X'0F' PSWPMSK FIXO+DECO+EXUN+SIGN
PROGRAM MASK
.... 1... PSWFIXO X'08' PSWFIXO FIXED-PT OVERFLOW
INTRPT MASK
.... .1.. PSWDECO X'04' PSWDECO DECIMAL OVERFLOW
INTRPT MASK
.... ..1. PSWEXUN X'02' PSWEXUN EXPONENT UNDERFLOW
INTRPT MASK
.... ...1 PSWSIGN X'01' PSWSIGN SIGNIFICANCE
INTERRUPT MASK
.... .... PSWPMODE X'00' PSWPMODE PRIMARY-SPACE MODE
005B 91 Bitstring 1 PFXEXTN3 EXT NEW PSW BYTE 3
005C 92 Signed 4 PFXEXTNI (0) EXT NEW PSW INSTRUCTION COUNTER
005C 92 Bitstring 1 PFXEXTN4 EXT NEW PSW BYTE 4
1... .... PSW31BT X'80' PSW31BT 31-BIT LOGICAL
ADDRESSING MODE
1... .... PSWBA PSW31BT PSWBA Basic Addressing
Mode
.111 1111 PSWHIADR X'7F' PSWHIADR INSTRUCTION
COUNTER BITS 1-7 - MUST BE ZERO
IN 24-BIT MODE.
.... .... PSW31AMF X'80000000' PSW31AMF ADDRESS MODE
FULLWORD MASK - CORRESPONDS TO
PSW31BT
005D 93 Bitstring 1 * (3) EXT NEW PSW BYTES 5-7
0060 96 Bitstring 1 PFXSVCN0 SVC NEW PSW BYTE 0
.1.. .... PSWPERA X'40' PSWPERA PROGRAM EVENT
RECORDING ACTIVE
.... .1.. PSWTRAN X'04' PSWTRAN ADDRESS TRANSLATE
MODE ACTIVE
.... ..1. PSWIOSM X'02' PSWIOSM I/O INTERRUPTION
SUMMARY MASK
.... ...1 PSWEXSM X'01' PSWEXSM EXTERNAL INTERRUPT
SUMMARY MASK
0061 97 Bitstring 1 PFXSVCN1 SVC NEW PSW BYTE 1
1111 .... PSWKEY X'F0' PSWKEY PSW ACCESS KEY
EXTRACTION MASK
.... 1... PSWECMD X'08' PSWECMD EXTENDED CONTROL
MODE ACTIVE
.... .1.. PSWMCHK X'04' PSWMCHK MACHINE CHECK
SUMMARY MASK
.... ..1. PSWWAIT X'02' PSWWAIT PROGRAM WAIT STATE
.... ...1 PSWPROB X'01' PSWPROB PROGRAM PROBLEM
STATE
.... ...1 PSWMAPPD X'01' PSWMAPPD For BC-mode PSWs
created by the 370 Accommodation
facility, this bit being set
indicates that the PSW is really
a "mapped" PSW. See HCPPSW.
0062 98 Bitstring 1 PFXSVCN2 SVC NEW PSW BYTE 2
11.. .... PSWASMSK X'C0' PSWASMSK ADDRESS SPACE
CONTROL MASK
11.. .... PSWHMODE X'C0' PSWHMODE HOME-SPACE MODE
1... .... PSWSMODE X'80' PSWSMODE SECONDARY MODE
.1.. .... PSWAMODE X'40' PSWAMODE ACCESS-REGISTER
MODE
..11 .... PSWCOND X'30' PSWCOND PSW CONDITION CODE
..1. .... PSWCOND2 X'20' PSWCOND2 PSW CONDITION CODE
BIT FOR CC=2,3
...1 .... PSWCOND1 X'10' PSWCOND1 PSW CONDITION CODE
BIT FOR CC=1,3
.... 1111 PSWPMSK X'0F' PSWPMSK FIXO+DECO+EXUN+SIGN
PROGRAM MASK
.... 1... PSWFIXO X'08' PSWFIXO FIXED-PT OVERFLOW
INTRPT MASK
.... .1.. PSWDECO X'04' PSWDECO DECIMAL OVERFLOW
INTRPT MASK
.... ..1. PSWEXUN X'02' PSWEXUN EXPONENT UNDERFLOW
INTRPT MASK
.... ...1 PSWSIGN X'01' PSWSIGN SIGNIFICANCE
INTERRUPT MASK
.... .... PSWPMODE X'00' PSWPMODE PRIMARY-SPACE MODE
0063 99 Bitstring 1 PFXSVCN3 SVC NEW PSW BYTE 3
0064 100 Signed 4 PFXSVCNI (0) SVC NEW PSW INSTRUCTION COUNTER
0064 100 Bitstring 1 PFXSVCN4 SVC NEW PSW BYTE 4
1... .... PSW31BT X'80' PSW31BT 31-BIT LOGICAL
ADDRESSING MODE
1... .... PSWBA PSW31BT PSWBA Basic Addressing
Mode
.111 1111 PSWHIADR X'7F' PSWHIADR INSTRUCTION
COUNTER BITS 1-7 - MUST BE ZERO
IN 24-BIT MODE.
.... .... PSW31AMF X'80000000' PSW31AMF ADDRESS MODE
FULLWORD MASK - CORRESPONDS TO
PSW31BT
0065 101 Bitstring 1 * (3) SVC NEW PSW BYTES 5-7
0068 104 Bitstring 1 PFXPRGN0 PRG NEW PSW BYTE 0
.1.. .... PSWPERA X'40' PSWPERA PROGRAM EVENT
RECORDING ACTIVE
.... .1.. PSWTRAN X'04' PSWTRAN ADDRESS TRANSLATE
MODE ACTIVE
.... ..1. PSWIOSM X'02' PSWIOSM I/O INTERRUPTION
SUMMARY MASK
.... ...1 PSWEXSM X'01' PSWEXSM EXTERNAL INTERRUPT
SUMMARY MASK
0069 105 Bitstring 1 PFXPRGN1 PRG NEW PSW BYTE 1
1111 .... PSWKEY X'F0' PSWKEY PSW ACCESS KEY
EXTRACTION MASK
.... 1... PSWECMD X'08' PSWECMD EXTENDED CONTROL
MODE ACTIVE
.... .1.. PSWMCHK X'04' PSWMCHK MACHINE CHECK
SUMMARY MASK
.... ..1. PSWWAIT X'02' PSWWAIT PROGRAM WAIT STATE
.... ...1 PSWPROB X'01' PSWPROB PROGRAM PROBLEM
STATE
.... ...1 PSWMAPPD X'01' PSWMAPPD For BC-mode PSWs
created by the 370 Accommodation
facility, this bit being set
indicates that the PSW is really
a "mapped" PSW. See HCPPSW.
006A 106 Bitstring 1 PFXPRGN2 PRG NEW PSW BYTE 2
11.. .... PSWASMSK X'C0' PSWASMSK ADDRESS SPACE
CONTROL MASK
11.. .... PSWHMODE X'C0' PSWHMODE HOME-SPACE MODE
1... .... PSWSMODE X'80' PSWSMODE SECONDARY MODE
.1.. .... PSWAMODE X'40' PSWAMODE ACCESS-REGISTER
MODE
..11 .... PSWCOND X'30' PSWCOND PSW CONDITION CODE
..1. .... PSWCOND2 X'20' PSWCOND2 PSW CONDITION CODE
BIT FOR CC=2,3
...1 .... PSWCOND1 X'10' PSWCOND1 PSW CONDITION CODE
BIT FOR CC=1,3
.... 1111 PSWPMSK X'0F' PSWPMSK FIXO+DECO+EXUN+SIGN
PROGRAM MASK
.... 1... PSWFIXO X'08' PSWFIXO FIXED-PT OVERFLOW
INTRPT MASK
.... .1.. PSWDECO X'04' PSWDECO DECIMAL OVERFLOW
INTRPT MASK
.... ..1. PSWEXUN X'02' PSWEXUN EXPONENT UNDERFLOW
INTRPT MASK
.... ...1 PSWSIGN X'01' PSWSIGN SIGNIFICANCE
INTERRUPT MASK
.... .... PSWPMODE X'00' PSWPMODE PRIMARY-SPACE MODE
006B 107 Bitstring 1 PFXPRGN3 PRG NEW PSW BYTE 3
006C 108 Signed 4 PFXPRGNI (0) PRG NEW PSW INSTRUCTION COUNTER
006C 108 Bitstring 1 PFXPRGN4 PRG NEW PSW BYTE 4
1... .... PSW31BT X'80' PSW31BT 31-BIT LOGICAL
ADDRESSING MODE
1... .... PSWBA PSW31BT PSWBA Basic Addressing
Mode
.111 1111 PSWHIADR X'7F' PSWHIADR INSTRUCTION
COUNTER BITS 1-7 - MUST BE ZERO
IN 24-BIT MODE.
.... .... PSW31AMF X'80000000' PSW31AMF ADDRESS MODE
FULLWORD MASK - CORRESPONDS TO
PSW31BT
006D 109 Bitstring 1 * (3) PRG NEW PSW BYTES 5-7
0070 112 Bitstring 1 PFXMCHN0 MCH NEW PSW BYTE 0
.1.. .... PSWPERA X'40' PSWPERA PROGRAM EVENT
RECORDING ACTIVE
.... .1.. PSWTRAN X'04' PSWTRAN ADDRESS TRANSLATE
MODE ACTIVE
.... ..1. PSWIOSM X'02' PSWIOSM I/O INTERRUPTION
SUMMARY MASK
.... ...1 PSWEXSM X'01' PSWEXSM EXTERNAL INTERRUPT
SUMMARY MASK
0071 113 Bitstring 1 PFXMCHN1 MCH NEW PSW BYTE 1
1111 .... PSWKEY X'F0' PSWKEY PSW ACCESS KEY
EXTRACTION MASK
.... 1... PSWECMD X'08' PSWECMD EXTENDED CONTROL
MODE ACTIVE
.... .1.. PSWMCHK X'04' PSWMCHK MACHINE CHECK
SUMMARY MASK
.... ..1. PSWWAIT X'02' PSWWAIT PROGRAM WAIT STATE
.... ...1 PSWPROB X'01' PSWPROB PROGRAM PROBLEM
STATE
.... ...1 PSWMAPPD X'01' PSWMAPPD For BC-mode PSWs
created by the 370 Accommodation
facility, this bit being set
indicates that the PSW is really
a "mapped" PSW. See HCPPSW.
0072 114 Bitstring 1 PFXMCHN2 MCH NEW PSW BYTE 2
11.. .... PSWASMSK X'C0' PSWASMSK ADDRESS SPACE
CONTROL MASK
11.. .... PSWHMODE X'C0' PSWHMODE HOME-SPACE MODE
1... .... PSWSMODE X'80' PSWSMODE SECONDARY MODE
.1.. .... PSWAMODE X'40' PSWAMODE ACCESS-REGISTER
MODE
..11 .... PSWCOND X'30' PSWCOND PSW CONDITION CODE
..1. .... PSWCOND2 X'20' PSWCOND2 PSW CONDITION CODE
BIT FOR CC=2,3
...1 .... PSWCOND1 X'10' PSWCOND1 PSW CONDITION CODE
BIT FOR CC=1,3
.... 1111 PSWPMSK X'0F' PSWPMSK FIXO+DECO+EXUN+SIGN
PROGRAM MASK
.... 1... PSWFIXO X'08' PSWFIXO FIXED-PT OVERFLOW
INTRPT MASK
.... .1.. PSWDECO X'04' PSWDECO DECIMAL OVERFLOW
INTRPT MASK
.... ..1. PSWEXUN X'02' PSWEXUN EXPONENT UNDERFLOW
INTRPT MASK
.... ...1 PSWSIGN X'01' PSWSIGN SIGNIFICANCE
INTERRUPT MASK
.... .... PSWPMODE X'00' PSWPMODE PRIMARY-SPACE MODE
0073 115 Bitstring 1 PFXMCHN3 MCH NEW PSW BYTE 3
0074 116 Signed 4 PFXMCHNI (0) MCH NEW PSW INSTRUCTION COUNTER
0074 116 Bitstring 1 PFXMCHN4 MCH NEW PSW BYTE 4
1... .... PSW31BT X'80' PSW31BT 31-BIT LOGICAL
ADDRESSING MODE
1... .... PSWBA PSW31BT PSWBA Basic Addressing
Mode
.111 1111 PSWHIADR X'7F' PSWHIADR INSTRUCTION
COUNTER BITS 1-7 - MUST BE ZERO
IN 24-BIT MODE.
.... .... PSW31AMF X'80000000' PSW31AMF ADDRESS MODE
FULLWORD MASK - CORRESPONDS TO
PSW31BT
0075 117 Bitstring 1 * (3) MCH NEW PSW BYTES 5-7
0078 120 Bitstring 1 PFXIOPN0 I/O NEW PSW BYTE 0
.1.. .... PSWPERA X'40' PSWPERA PROGRAM EVENT
RECORDING ACTIVE
.... .1.. PSWTRAN X'04' PSWTRAN ADDRESS TRANSLATE
MODE ACTIVE
.... ..1. PSWIOSM X'02' PSWIOSM I/O INTERRUPTION
SUMMARY MASK
.... ...1 PSWEXSM X'01' PSWEXSM EXTERNAL INTERRUPT
SUMMARY MASK
0079 121 Bitstring 1 PFXIOPN1 I/O NEW PSW BYTE 1
1111 .... PSWKEY X'F0' PSWKEY PSW ACCESS KEY
EXTRACTION MASK
.... 1... PSWECMD X'08' PSWECMD EXTENDED CONTROL
MODE ACTIVE
.... .1.. PSWMCHK X'04' PSWMCHK MACHINE CHECK
SUMMARY MASK
.... ..1. PSWWAIT X'02' PSWWAIT PROGRAM WAIT STATE
.... ...1 PSWPROB X'01' PSWPROB PROGRAM PROBLEM
STATE
.... ...1 PSWMAPPD X'01' PSWMAPPD For BC-mode PSWs
created by the 370 Accommodation
facility, this bit being set
indicates that the PSW is really
a "mapped" PSW. See HCPPSW.
007A 122 Bitstring 1 PFXIOPN2 I/O NEW PSW BYTE 2
11.. .... PSWASMSK X'C0' PSWASMSK ADDRESS SPACE
CONTROL MASK
11.. .... PSWHMODE X'C0' PSWHMODE HOME-SPACE MODE
1... .... PSWSMODE X'80' PSWSMODE SECONDARY MODE
.1.. .... PSWAMODE X'40' PSWAMODE ACCESS-REGISTER
MODE
..11 .... PSWCOND X'30' PSWCOND PSW CONDITION CODE
..1. .... PSWCOND2 X'20' PSWCOND2 PSW CONDITION CODE
BIT FOR CC=2,3
...1 .... PSWCOND1 X'10' PSWCOND1 PSW CONDITION CODE
BIT FOR CC=1,3
.... 1111 PSWPMSK X'0F' PSWPMSK FIXO+DECO+EXUN+SIGN
PROGRAM MASK
.... 1... PSWFIXO X'08' PSWFIXO FIXED-PT OVERFLOW
INTRPT MASK
.... .1.. PSWDECO X'04' PSWDECO DECIMAL OVERFLOW
INTRPT MASK
.... ..1. PSWEXUN X'02' PSWEXUN EXPONENT UNDERFLOW
INTRPT MASK
.... ...1 PSWSIGN X'01' PSWSIGN SIGNIFICANCE
INTERRUPT MASK
.... .... PSWPMODE X'00' PSWPMODE PRIMARY-SPACE MODE
007B 123 Bitstring 1 PFXIOPN3 I/O NEW PSW BYTE 3
007C 124 Signed 4 PFXIOPNI (0) I/O NEW PSW INSTRUCTION COUNTER
007C 124 Bitstring 1 PFXIOPN4 I/O NEW PSW BYTE 4
1... .... PSW31BT X'80' PSW31BT 31-BIT LOGICAL
ADDRESSING MODE
1... .... PSWBA PSW31BT PSWBA Basic Addressing
Mode
.111 1111 PSWHIADR X'7F' PSWHIADR INSTRUCTION
COUNTER BITS 1-7 - MUST BE ZERO
IN 24-BIT MODE.
.... .... PSW31AMF X'80000000' PSW31AMF ADDRESS MODE
FULLWORD MASK - CORRESPONDS TO
PSW31BT
007D 125 Bitstring 1 * (3) I/O NEW PSW BYTES 5-7
00E8 232 Bitstring 1 PFXMCHI0 MACHINE CHECK INTERRUPT CODE BYTE
0
1111 1111 MCIPRIM0 X'FF' MCIPRIM0 PRIMARY MACHINE
CHECK BITS - BYTE 0
1... .... MCICSD X'80' MCICSD SYSTEM DAMAGE BIT.
.1.. .... MCICPD X'40' MCICPD PROCESSING DAMAGE
BIT.
..1. .... MCICSR X'20' MCICSR SYSTEM RECOVERY BIT.
...1 .... MCICITD X'10' MCICITD INTERVAL TIMER
DAMAGE. (370 GUESTS)
.... 1... MCICCD X'08' MCICCD TIMING (CLOCK)
FACILITY DAMAGE.
.... .1.. MCICED X'04' MCICED EXTERNAL DAMAGE.
.... ...1 MCICDG X'01' MCICDG DEGRADATION BIT.
00E9 233 Bitstring 1 PFXMCHI1 MACHINE CHECK INTERRUPT CODE BYTE
1
1111 .... MCIPRIM1 X'F0' MCIPRIM1 PRIMARY MACHINE
CHECK BITS - BYTE 1
1... .... MCICW X'80' MCICW WARNING BIT.
.1.. .... MCICCRW X'40' MCICCRW PENDING-CRW REPORT.
..1. .... MCICSP X'20' MCICSP SERVICE PROCESSOR
DAMAGE.
...1 .... MCICCSD X'10' MCICCSD CHANNEL-SUBSYSTEM
DAMAGE.
.... ..1. MCICBU X'02' MCICBU 'BACKED UP' BIT.
.... ...1 MCICDL X'01' MCICDL 'DELAYED' BIT. (370
GUESTS)
00EA 234 Bitstring 1 PFXMCHI2 MACHINE CHECK INTERRUPT CODE BYTE
2
1... .... MCICSE X'80' MCICSE STORAGE ERROR
UNCORRECTED.
.1.. .... MCICSC X'40' MCICSC STORAGE ERROR
CORRECTED.
..1. .... MCICKE X'20' MCICKE STORAGE-KEY ERROR
UNCORRECTED.
...1 .... MCICSDG X'10' MCICSDG STORAGE
DEGRADATION. MODIFIES STORAGE
ERROR CORRECTED.
.... 1... MCICVWP X'08' MCICVWP BITS 12-15 OF MC
OLD PSW VALID.
.... .1.. MCICVMS X'04' MCICVMS SYSTEM MASK & KEY
OF MC OLD PSW VALID.
.... ..1. MCICVPM X'02' MCICVPM PROGRAM MASK & CC
OF MC OLD PSW VALID.
.... ...1 MCICVIA X'01' MCICVIA INSTR ADDR OF MC
OLD PSW IS VALID.
00EB 235 Bitstring 1 PFXMCHI3 MACHINE CHECK INTERRUPT CODE BYTE
3
1... .... MCICVFA X'80' MCICVFA FAILING STORAGE
ADDRESS IS VALID.
.1.. .... MCICVVR X'40' MCICVVR Vector Registers
stored are valid
..1. .... MCICVED X'20' MCICVED EXTERNAL-DAMAGE
CODE IS VALID.
...1 .... MCICVFP X'10' MCICVFP FP REGISTERS STORED
ARE VALID.
.... 1... MCICVGR X'08' MCICVGR GP REGISTERS STORED
ARE VALID.
.... .1.. MCICVCR X'04' MCICVCR CONTROL REGISTERS
STORED VALID.
.... ..1. MCIC30 X'02' MCIC30 MCIC.30
.... ...1 MCICVST X'01' MCICVST INST. MODIFIED
STORAGE IS VALID.
00EC 236 Bitstring 1 PFXMCHI4 MACHINE CHECK INTERRUPT CODE BYTE
4
1... .... MCICIE X'80' MCICIE INDIRECT STORAGE
ERROR
.1.. .... MCICVAR X'40' MCICVAR ACCESS REGISTERS
STORED ARE VALID
..1. .... MCICDA X'20' MCICDA DELAYED ACCESS
EXCEPTION BIT
.... 1... MCICVGS X'08' MCICVGS Guarded Storage
regs stored are valid
.... .1.. MCICVBEA X'04' MCICVBEA
Breaking-event-address reg. is
valid
00ED 237 Bitstring 1 PFXMCHI5 MACHINE CHECK INTERRUPT CODE BYTE
5
..1. .... MCICVTPR X'20' MCICVTPR TOD programmable
register validity
...1 .... MCICVXFP X'10' MCICVXFP Additional FP
Registers Validity (ESA390) FP
Control Register Validity (zArch)
.... 1... MCICAR X'08' MCICAR Ancillary Report Bit
.... ..1. MCICVCT X'02' MCICVCT CPU TIMER STORED IS
VALID.
.... ...1 MCICVCC X'01' MCICVCC CLOCK COMPARATOR
STORED IS VALID.
00EE 238 Bitstring 2 PFXMCHI6 MACHINE CHECK INTERRUPT CODE BYTE
6-7
00F4 244 Bitstring 1 PFXDCBY0 Byte 0 of the external damage
code
.... .... MCEXTD0 X'00' MCEXTD0 No bits defined
00F5 245 Bitstring 1 PFXDCBY1 Byte 1 of the external damage
code
.... .... MCEXTD1 X'00' MCEXTD1 No bits defined
00F6 246 Bitstring 1 PFXDCBY2 Byte 2 of the external damage
code
...1 .... MCEXTDSC X'10' MCEXTDSC Bit 19 - ETR Sync
check
00F7 247 Bitstring 1 PFXDCBY3 Byte 3 of the external damage
code
1... .... MCEXTDSS X'80' MCEXTDSS Bit 24 - STP Sync
Check
.1.. .... MCEXTDIC X'40' MCEXTDIC Bit 25 - Island
Condition
..1. .... MCEXTDCC X'20' MCEXTDCC Bit 26 - CTN
Configuration Change
...1 .... MCEXTDCS X'10' MCEXTDCS Bit 27 - STP Clock
Source Error
0100 256 Dbl-Word 8 PFXSTPSW STORE STATUS PSW LOGOUT AREA
0108 264 Signed 4 PFXSTPFX STORE STATUS PREFIX LOGOUT AREA
010C 268 Signed 4 PFXSTMDL STORE STATUS MODEL DEPENDENT DATA
0160 352 Dbl-Word 8 PFXFPRY0 Floating Point Register 0
0168 360 Dbl-Word 8 PFXFPRY2 Floating Point Register 2
0170 368 Dbl-Word 8 PFXFPRY4 Floating Point Register 4
0178 376 Dbl-Word 8 PFXFPRY6 Floating Point Register 6
** Start of section zeroed during alternate
** processor init. Updates to this section
** should also hit ncPFXFMPB in module HCPMPS.
00000200 PFXZALT * Start of zeroed section.
The following fields are used by the Paging fast path.
0200 512 Signed 4 PFXCLPLCnt Count of frames on the cleared
local available list plus the
count of frames on the firmware
processed list. Serialized
exclusively by CS.
Incremented/Decremented by the
local CPU when items are
added/removed from PFXCLAL.
Decremented by any CPU upon
completion of reaping and
processing the PFXfwPROCL.
0204 516 Address 4 * Reserved for IBM use
The following fields are architected for use by both
firmware and software. Their displacements must not be
changed.
0208 520 Address 8 PFXfwPROCL Processed list anchor See HCPHTT
for comments.
0210 528 Address 8 PFXCLALPtr Cleared Local Available List. See
HCPHTT for comments.
0218 536 Address 8 PFXAFOBL Available-FOB list origin.
0220 544 Signed 4 PFXAFOBC Available-FOB list count.
0224 548 Signed 4 * Reserved for IBM use
0228 552 Dbl-Word 8 PFXDPPCAO Origin pointer to the class 1
Delta-pinned-page-count array.
The class 1 DPPCA resides in
RSMBK (RSMDPPB/RSMDPPA)
0230 560 Dbl-Word 8 * (2) Reserved for IBM use
End of architected fields section
0240 576 Signed 2 * Reserved for IBM use (was
PFXLAVFU)
0242 578 Signed 2 * Reserved for IBM use (was
PFXLAVDF)
0244 580 Signed 2 * Reserved for IBM use (was
PFXLAVU)
0246 582 Bitstring 1 PFXGPFLG General purpose flag
1... .... PFX2GU X'80' PFX2GU Usable storage
exists for the >= 2G available
list
0247 583 Bitstring 1 * Reserved for IBM use
0248 584 Signed 8 * Reserved for IBM use (was
PFXLAVAU)
00000050 PFXZALTL *-PFXZALT Length of block
** End of section zeroed during alternate processor init
Frame Table management area.
0250 592 Address 8 PFXFTBLG Origin of Frame Table This is a
host logical address >2G.
0258 600 Address 8 PFX2GFTE Address of FRMTE for the frame
with address 2G. If there is no
frame with address 2G, this is
where the FRMTE would be. This is
a host logical address >2G.
0260 608 Signed 8 PFXFTLEN Length of Frame Table
SXS Page Management Table attributes.
0268 616 Address 8 PFXSTBLG Origin of SXS Page Mgt Table.
This is a host logical address.
0270 624 Signed 8 PFXSTLEN Length of SXS Page Mgt Table
Software Last-Translated Address Lookaside Buffer area.
NOTES : For 5.1.0, the use of this buffer changes
from: Fast Translation to HOST REAL ADDRESS
to: Fast Translation to HOST LOGICAL ADDRESS
As a result, PFXGLFRA is being renamed to PFXGLSXP.
If it is decided to use this buffer for Fast Translations
to HOST LOGICAL ADDRESS AND HOST ABSOLUTE ADDRESS, then
a 64-bit PFXGLFRA field will need to be added for the
HOST ABSOLUTE translations.
PFXGLFRA DS 0F Last translated frame address
Notes : Buffer path reads and translation updates are done
in opposite order so there is no safe order for
reach across clearing of the SLTALB. If reach
across clearing of the SLTALB is to be done, it
must be done using CDSG logic to guarentee that
the clearing will not leave PFXGLPAG in the
cleared state without PGXGLPAS also being cleared.
0278 632 Dbl-Word 8 PFXSLTLB (3) Software Last-Translated
LookAside Buffer
0278 632 Signed 4 * Reserved for future IBM use
027C 636 Signed 4 PFXGLSXP Last translated SXS Page Address
The next two fields must be
together on a quadword coundary
0280 640 Dbl-Word 8 PFXGLPAG Last translated guest page
0280 640 Signed 4 PFXGLPW0 Word 0 of last translated guest
page
0284 644 Signed 4 PFXGLPW1 Word 1 of last translated guest
page
0288 648 Dbl-Word 8 PFXGLPAS Last translated primary ASCE
0288 648 Signed 4 PFXGLAW0 Word 0 of last translated primary
ASCE
028C 652 Signed 4 PFXGLAW1 Word 1 of last translated primary
ASCE
Address Space Control Elements (ASCEs) and Access List
Entry Tokens (ALETs) for frequently used System owned
permanent spaces. Note that we don't save an ASCE for the
Real Space, since it's just a doubleword of zeros with the
R bit set. We don't have an ALET for the System Execution
Space (SXS) because it will be the primary space when in
AR-mode, so use ALETPRIM to load the access registers.
0290 656 Address 8 PFXSXASC System Execution Space ASCE
(Address Space Control Element)
0290 656 Signed 4 PFXXASW0 Word 0 of System Execution Space
ASCE
0294 660 Signed 4 PFXXASW1 Word 1 of System Execution Space
ASCE
0298 664 Address 8 PFXNASCE ASCE for "null" address space
PFXNASCE PFXNASW0 00004 PFXNASCE+0,4 Word 0 of
"null" space ASCE
PFXNASCE PFXNASW1 00004 PFXNASCE+4,4 Word 1 of
"null" space ASCE
02A0 672 Signed 4 * Reserved for IBM use
02A4 676 Signed 4 PFXRSAL Real Space ALET
02A8 680 Dbl-Word 8 * (3) Reserved for future IBM use
PFXSAVES - savearea region
0300 768 Bitstring 256 PFXTMPSG (0) Temporary Save Area (Large)
0300 768 Bitstring 128 PFXTMPSV TEMPORARY SAVE AREA
0380 896 Bitstring 128 *
0400 1024 Bitstring 256 PFXWRKSG (0) Special Work Save Area (Large)
0400 1024 Bitstring 128 PFXWRKSV SPECIAL WORK SAVE AREA
0480 1152 Bitstring 128 *
0500 1280 Bitstring 256 PFXBALSG (0) BALR Linkage Save Area (Large)
0500 1280 Bitstring 128 PFXBALSV BALR LINKAGE SAVE AREA
0580 1408 Bitstring 128 *
0600 1536 Bitstring 256 PFXPTRSG (0) BALR Linkage Save Area (Large)
0600 1536 Bitstring 128 PFXPTRSV PAGE TRANSLATION SAVE AREA
0680 1664 Bitstring 128 *
0700 1792 Bitstring 256 PFXFRESG (0) HCPFRE Save Area (Large)
0700 1792 Bitstring 128 PFXFRESV HCPFRE SAVE AREA
0780 1920 Bitstring 128 *
0800 2048 Bitstring 32 PFXIRPSG (0) R12-R15 Save Area for FLIHs
(Large)
0800 2048 Bitstring 16 PFXIRPSV R12-R15 SAVE AREA FOR FLIHS
0810 2064 Bitstring 16 *
0820 2080 Bitstring 32 PFXLNKSG (0) Call/Return Linkage Save Area
(Large)
0820 2080 Bitstring 16 PFXLNKSV CP CALL/RETURN LINKAGE SAVEAREA
0830 2096 Bitstring 16 *
0840 2112 Bitstring 128 PFXSVCSG (0) SVC R0-R15 Save Area (Large)
0840 2112 Bitstring 64 PFXSVCSV SVC R0-R15 savearea
0880 2176 Bitstring 64 *
08C0 2240 Address 4 PFXSVC HCPSVC address
08C4 2244 Address 4 PFXLRQND A(last freed SAVBK) only if
&HCPDBG
08C8 2248 Signed 4 PFXLRC Local SAVBK return queue count
08CC 2252 Address 4 PFXLRQ Local SAVBK return queue PFXLRC
and PFXLRQ should be in the same
d-word for fastest access.
08D0 2256 Address 4 PFXCPRQA Cross processor return queue
addr. Bit 0 of this word may be
used as a flag. Be careful when
using this field when in Amode64.
08D4 2260 Address 4 PFXCPRQP Cross processor return queue
addr. Bit 0 of this word may be
used as a flag. Be careful when
using this field when in Amode64.
08D8 2264 Address 4 PFXSSABK Static savearea pointer
08DC 2268 Address 4 PFX2WAY A(current STATIC savearea)
08E0 2272 Address 4 PFXSVU HCPSVU address
08E4 2276 Address 4 PFXSVF HCPSVF address
08E8 2280 Address 8 PFXSVR13 Temporary R13 save for SSABK
usage
08F0 2288 Signed 2 * Reserved for IBM use
08F2 2290 Bitstring 1 PFXIACR Caller IAC for linkage PFXIACR
should remain at byte 2 within
its word in storage so that
HCPCALL can use L PFXIACR-2 to
get the field into byte 6 of the
register for subsequent SACF
0(Rx).
08F3 2291 Bitstring 1 PFXIACE Callee IAC for linkage
Bytes for various and sundry debug trap operations.
Fullword aligned to avoid error messages if L is used.
08F4 2292 Signed 4 * (0)
08F4 2292 Bitstring 1 PFXSVFW0 HCPSVF CC work area
08F5 2293 Bitstring 1 PFXSVFW1 HCPSVF STNSM/SSM work area
08F6 2294 Bitstring 1 PFXSVFW2 Reserved for IBM use
08F7 2295 Bitstring 1 PFXSVFW3 Reserved for IBM use
08F8 2296 Dbl-Word 8 PFXDBGRX 1-register save for debug things
THIS AREA HAS THE SAME FORMAT AS A SAVEAREA IN HCPSAVBK
0300 768 Signed 4 PFXTMPFP
0304 772 Signed 4 PFXTMPBP
0308 776 Signed 4 *
030C 780 Signed 4 *
0310 784 Bitstring 1 PFXTMPSC
0311 785 Bitstring 1 PFXTMPCL
0312 786 Bitstring 1 *
0313 787 Bitstring 1 *
0314 788 Signed 4 *
0318 792 Bitstring 232 PFXTMPAREA (0) Register and working storage
0318 792 Bitstring 64 PFXTMPRG (0) Caller's registers
0318 792 Signed 4 PFXTMPR0 (0) Caller's saved register 0
0318 792 Bitstring 1 PFXTMPR0B0 byte 0
0319 793 Bitstring 1 PFXTMPR0B1 byte 1
031A 794 Bitstring 1 PFXTMPR0B2 byte 2
031B 795 Bitstring 1 PFXTMPR0B3 byte 3
031C 796 Signed 4 PFXTMPR1 (0) Caller's saved register 1
031C 796 Bitstring 1 PFXTMPR1B0 byte 0
031D 797 Bitstring 1 PFXTMPR1B1 byte 1
031E 798 Bitstring 1 PFXTMPR1B2 byte 2
031F 799 Bitstring 1 PFXTMPR1B3 byte 3
0320 800 Signed 4 PFXTMPR2 (0) Caller's saved register 2 THE
FOLLOWING BYTE DEFINITIONS OF
SAVER2 ARE FOR TESTING PARAMETERS
PASSED BETWEEN MODULES.
0320 800 Bitstring 1 PFXTMPR2B0 byte 0
0321 801 Bitstring 1 PFXTMPR2B1 byte 1
0322 802 Bitstring 1 PFXTMPR2B2 byte 2
0323 803 Bitstring 1 PFXTMPR2B3 byte 3
0324 804 Signed 4 PFXTMPR3 Caller's saved register 3
0328 808 Signed 4 PFXTMPR4 Caller's saved register 4
032C 812 Signed 4 PFXTMPR5 Caller's saved register 5
0330 816 Signed 4 PFXTMPR6 Caller's saved register 6
0334 820 Signed 4 PFXTMPR7 Caller's saved register 7
0338 824 Signed 4 PFXTMPR8 Caller's saved register 8
033C 828 Signed 4 PFXTMPR9 Caller's saved register 9
0340 832 Signed 4 PFXTMPRA Caller's saved register 10
0344 836 Signed 4 PFXTMPRB Caller's saved register 11; ALSO
VMDBK ADDRESS OF USER ON WHICH
SAVBK IS SCHEDULED
0348 840 Bitstring 16 PFXTMPRCF (0) Caller's saved register 12-15
0348 840 Signed 4 PFXTMPRC Caller's saved register 12
034C 844 Signed 4 PFXTMPRD Caller's saved register 13; ALSO
PREVIOUS SAVBK ADDRESS ON CALL
0350 848 Signed 4 PFXTMPRE Caller's saved register 14; ALSO
RETURN ADDRESS ON CALL OR STACKED
SAVBK RETURN
0354 852 Signed 4 PFXTMPRF Caller's saved register 15; ALSO
GOTO ADDRESS ON SCHEDULED SAVBK
EXECUTION; ALSO REGISTER 15
RETURN CODE ON HCPEXIT OR STACKED
SAVBK RETURN
0358 856 Bitstring 40 PFXTMPWK (0) Workarea for callee
0358 856 Signed 4 PFXTMPW0
035C 860 Signed 4 PFXTMPW1
0360 864 Signed 4 PFXTMPW2
0364 868 Signed 4 PFXTMPW3
0368 872 Signed 4 PFXTMPW4
036C 876 Signed 4 PFXTMPW5
0370 880 Signed 4 PFXTMPW6
0374 884 Signed 4 PFXTMPW7
0378 888 Signed 4 PFXTMPW8
037C 892 Signed 4 PFXTMPW9
0380 896 Bitstring 1 PFXTMPW$ (0)
SAVBK extension: Saveareas in the
SAVBK format *may* have the high halves of
registers stored in the tail end. Bit SAVERG64 in the
savearea header indicates that these fields are valid.
0380 896 Signed 4 * (4) Reserved for future use
0390 912 Signed 4 * (4) Reserved for future use
The SAVBK SAVEAARP and the SVGBK SVGAARP fields must be
at the same offset into each control block. The only
available area in both that satisfies this requirement
is, unfortunately, here in the middle of the control
block.
03A0 928 Address 4 PFXTMPOPNR A(who set SVHOPEN)
03A4 932 Signed 4 * Reserved for IBM use
03A8 936 Address 4 PFXTMPAARP A(AR sidecar) for PFX saveareas
03AC 940 Bitstring 1 PFXTMPIACA Caller actual IAC
03AD 941 Bitstring 1 PFXTMPAMDE Amode of callee at entry.
03AE 942 Bitstring 1 PFXTMPIACR Caller "should be" IAC
03AF 943 Bitstring 1 PFXTMPIACE Callee "should be" IAC
03B0 944 Signed 4 * (4) Reserved for future use
03C0 960 Bitstring 64 PFXTMPHIRG (0)
03C0 960 Signed 4 PFXTMPH0 High word of zArch general reg 0
03C4 964 Signed 4 PFXTMPH1 High word of zArch general reg 1
03C8 968 Signed 4 PFXTMPH2 High word of zArch general reg 2
03CC 972 Signed 4 PFXTMPH3 High word of zArch general reg 3
03D0 976 Signed 4 PFXTMPH4 High word of zArch general reg 4
03D4 980 Signed 4 PFXTMPH5 High word of zArch general reg 5
03D8 984 Signed 4 PFXTMPH6 High word of zArch general reg 6
03DC 988 Signed 4 PFXTMPH7 High word of zArch general reg 7
03E0 992 Signed 4 PFXTMPH8 High word of zArch general reg 8
03E4 996 Signed 4 PFXTMPH9 High word of zArch general reg 9
03E8 1000 Signed 4 PFXTMPH10 High word of zArch general reg 10
03EC 1004 Signed 4 PFXTMPH11 High word of zArch general reg 11
03F0 1008 Signed 4 PFXTMPH12 High word of zArch general reg 12
03F4 1012 Signed 4 PFXTMPH13 High word of zArch general reg 13
03F8 1016 Signed 4 PFXTMPH14 High word of zArch general reg 14
03FC 1020 Signed 4 PFXTMPH15 High word of zArch general reg 15
03A8 936 Bitstring 4 * A(AR SIDECAR) FOR PFX SAVEAREA
THIS AREA HAS THE SAME FORMAT AS A SAVEAREA IN HCPSAVBK
0400 1024 Signed 4 PFXWRKFP
0404 1028 Signed 4 PFXWRKBP
0408 1032 Signed 4 *
040C 1036 Signed 4 *
0410 1040 Bitstring 1 PFXWRKSC
0411 1041 Bitstring 1 PFXWRKCL
0412 1042 Bitstring 1 *
0413 1043 Bitstring 1 *
0414 1044 Signed 4 *
0418 1048 Bitstring 232 PFXWRKAREA (0) Register and working storage
0418 1048 Bitstring 64 PFXWRKRG (0) Caller's registers
0418 1048 Signed 4 PFXWRKR0 (0) Caller's saved register 0
0418 1048 Bitstring 1 PFXWRKR0B0 byte 0
0419 1049 Bitstring 1 PFXWRKR0B1 byte 1
041A 1050 Bitstring 1 PFXWRKR0B2 byte 2
041B 1051 Bitstring 1 PFXWRKR0B3 byte 3
041C 1052 Signed 4 PFXWRKR1 (0) Caller's saved register 1
041C 1052 Bitstring 1 PFXWRKR1B0 byte 0
041D 1053 Bitstring 1 PFXWRKR1B1 byte 1
041E 1054 Bitstring 1 PFXWRKR1B2 byte 2
041F 1055 Bitstring 1 PFXWRKR1B3 byte 3
0420 1056 Signed 4 PFXWRKR2 (0) Caller's saved register 2 THE
FOLLOWING BYTE DEFINITIONS OF
SAVER2 ARE FOR TESTING PARAMETERS
PASSED BETWEEN MODULES.
0420 1056 Bitstring 1 PFXWRKR2B0 byte 0
0421 1057 Bitstring 1 PFXWRKR2B1 byte 1
0422 1058 Bitstring 1 PFXWRKR2B2 byte 2
0423 1059 Bitstring 1 PFXWRKR2B3 byte 3
0424 1060 Signed 4 PFXWRKR3 Caller's saved register 3
0428 1064 Signed 4 PFXWRKR4 Caller's saved register 4
042C 1068 Signed 4 PFXWRKR5 Caller's saved register 5
0430 1072 Signed 4 PFXWRKR6 Caller's saved register 6
0434 1076 Signed 4 PFXWRKR7 Caller's saved register 7
0438 1080 Signed 4 PFXWRKR8 Caller's saved register 8
043C 1084 Signed 4 PFXWRKR9 Caller's saved register 9
0440 1088 Signed 4 PFXWRKRA Caller's saved register 10
0444 1092 Signed 4 PFXWRKRB Caller's saved register 11; ALSO
VMDBK ADDRESS OF USER ON WHICH
SAVBK IS SCHEDULED
0448 1096 Bitstring 16 PFXWRKRCF (0) Caller's saved register 12-15
0448 1096 Signed 4 PFXWRKRC Caller's saved register 12
044C 1100 Signed 4 PFXWRKRD Caller's saved register 13; ALSO
PREVIOUS SAVBK ADDRESS ON CALL
0450 1104 Signed 4 PFXWRKRE Caller's saved register 14; ALSO
RETURN ADDRESS ON CALL OR STACKED
SAVBK RETURN
0454 1108 Signed 4 PFXWRKRF Caller's saved register 15; ALSO
GOTO ADDRESS ON SCHEDULED SAVBK
EXECUTION; ALSO REGISTER 15
RETURN CODE ON HCPEXIT OR STACKED
SAVBK RETURN
0458 1112 Bitstring 40 PFXWRKWK (0) Workarea for callee
0458 1112 Signed 4 PFXWRKW0
045C 1116 Signed 4 PFXWRKW1
0460 1120 Signed 4 PFXWRKW2
0464 1124 Signed 4 PFXWRKW3
0468 1128 Signed 4 PFXWRKW4
046C 1132 Signed 4 PFXWRKW5
0470 1136 Signed 4 PFXWRKW6
0474 1140 Signed 4 PFXWRKW7
0478 1144 Signed 4 PFXWRKW8
047C 1148 Signed 4 PFXWRKW9
0480 1152 Bitstring 1 PFXWRKW$ (0)
SAVBK extension: Saveareas in the
SAVBK format *may* have the high halves of
registers stored in the tail end. Bit SAVERG64 in the
savearea header indicates that these fields are valid.
0480 1152 Signed 4 * (4) Reserved for future use
0490 1168 Signed 4 * (4) Reserved for future use
The SAVBK SAVEAARP and the SVGBK SVGAARP fields must be
at the same offset into each control block. The only
available area in both that satisfies this requirement
is, unfortunately, here in the middle of the control
block.
04A0 1184 Address 4 PFXWRKOPNR A(who set SVHOPEN)
04A4 1188 Signed 4 * Reserved for IBM use
04A8 1192 Address 4 PFXWRKAARP A(AR sidecar) for PFX saveareas
04AC 1196 Bitstring 1 PFXWRKIACA Caller actual IAC
04AD 1197 Bitstring 1 PFXWRKAMDE Amode of callee at entry.
04AE 1198 Bitstring 1 PFXWRKIACR Caller "should be" IAC
04AF 1199 Bitstring 1 PFXWRKIACE Callee "should be" IAC
04B0 1200 Signed 4 * (4) Reserved for future use
04C0 1216 Bitstring 64 PFXWRKHIRG (0)
04C0 1216 Signed 4 PFXWRKH0 High word of zArch general reg 0
04C4 1220 Signed 4 PFXWRKH1 High word of zArch general reg 1
04C8 1224 Signed 4 PFXWRKH2 High word of zArch general reg 2
04CC 1228 Signed 4 PFXWRKH3 High word of zArch general reg 3
04D0 1232 Signed 4 PFXWRKH4 High word of zArch general reg 4
04D4 1236 Signed 4 PFXWRKH5 High word of zArch general reg 5
04D8 1240 Signed 4 PFXWRKH6 High word of zArch general reg 6
04DC 1244 Signed 4 PFXWRKH7 High word of zArch general reg 7
04E0 1248 Signed 4 PFXWRKH8 High word of zArch general reg 8
04E4 1252 Signed 4 PFXWRKH9 High word of zArch general reg 9
04E8 1256 Signed 4 PFXWRKH10 High word of zArch general reg 10
04EC 1260 Signed 4 PFXWRKH11 High word of zArch general reg 11
04F0 1264 Signed 4 PFXWRKH12 High word of zArch general reg 12
04F4 1268 Signed 4 PFXWRKH13 High word of zArch general reg 13
04F8 1272 Signed 4 PFXWRKH14 High word of zArch general reg 14
04FC 1276 Signed 4 PFXWRKH15 High word of zArch general reg 15
04A8 1192 Bitstring 4 * A(AR SIDECAR) FOR PFX SAVEAREA
THIS AREA HAS THE SAME FORMAT AS A SAVEAREA IN HCPSAVBK
0500 1280 Signed 4 PFXBALFP
0504 1284 Signed 4 PFXBALBP
0508 1288 Signed 4 *
050C 1292 Signed 4 *
0510 1296 Bitstring 1 PFXBALSC
0511 1297 Bitstring 1 PFXBALCL
0512 1298 Bitstring 1 *
0513 1299 Bitstring 1 *
0514 1300 Signed 4 *
0518 1304 Bitstring 232 PFXBALAREA (0) Register and working storage
0518 1304 Bitstring 64 PFXBALRG (0) Caller's registers
0518 1304 Signed 4 PFXBALR0 (0) Caller's saved register 0
0518 1304 Bitstring 1 PFXBALR0B0 byte 0
0519 1305 Bitstring 1 PFXBALR0B1 byte 1
051A 1306 Bitstring 1 PFXBALR0B2 byte 2
051B 1307 Bitstring 1 PFXBALR0B3 byte 3
051C 1308 Signed 4 PFXBALR1 (0) Caller's saved register 1
051C 1308 Bitstring 1 PFXBALR1B0 byte 0
051D 1309 Bitstring 1 PFXBALR1B1 byte 1
051E 1310 Bitstring 1 PFXBALR1B2 byte 2
051F 1311 Bitstring 1 PFXBALR1B3 byte 3
0520 1312 Signed 4 PFXBALR2 (0) Caller's saved register 2 THE
FOLLOWING BYTE DEFINITIONS OF
SAVER2 ARE FOR TESTING PARAMETERS
PASSED BETWEEN MODULES.
0520 1312 Bitstring 1 PFXBALR2B0 byte 0
0521 1313 Bitstring 1 PFXBALR2B1 byte 1
0522 1314 Bitstring 1 PFXBALR2B2 byte 2
0523 1315 Bitstring 1 PFXBALR2B3 byte 3
0524 1316 Signed 4 PFXBALR3 Caller's saved register 3
0528 1320 Signed 4 PFXBALR4 Caller's saved register 4
052C 1324 Signed 4 PFXBALR5 Caller's saved register 5
0530 1328 Signed 4 PFXBALR6 Caller's saved register 6
0534 1332 Signed 4 PFXBALR7 Caller's saved register 7
0538 1336 Signed 4 PFXBALR8 Caller's saved register 8
053C 1340 Signed 4 PFXBALR9 Caller's saved register 9
0540 1344 Signed 4 PFXBALRA Caller's saved register 10
0544 1348 Signed 4 PFXBALRB Caller's saved register 11; ALSO
VMDBK ADDRESS OF USER ON WHICH
SAVBK IS SCHEDULED
0548 1352 Bitstring 16 PFXBALRCF (0) Caller's saved register 12-15
0548 1352 Signed 4 PFXBALRC Caller's saved register 12
054C 1356 Signed 4 PFXBALRD Caller's saved register 13; ALSO
PREVIOUS SAVBK ADDRESS ON CALL
0550 1360 Signed 4 PFXBALRE Caller's saved register 14; ALSO
RETURN ADDRESS ON CALL OR STACKED
SAVBK RETURN
0554 1364 Signed 4 PFXBALRF Caller's saved register 15; ALSO
GOTO ADDRESS ON SCHEDULED SAVBK
EXECUTION; ALSO REGISTER 15
RETURN CODE ON HCPEXIT OR STACKED
SAVBK RETURN
0558 1368 Bitstring 40 PFXBALWK (0) Workarea for callee
0558 1368 Signed 4 PFXBALW0
055C 1372 Signed 4 PFXBALW1
0560 1376 Signed 4 PFXBALW2
0564 1380 Signed 4 PFXBALW3
0568 1384 Signed 4 PFXBALW4
056C 1388 Signed 4 PFXBALW5
0570 1392 Signed 4 PFXBALW6
0574 1396 Signed 4 PFXBALW7
0578 1400 Signed 4 PFXBALW8
057C 1404 Signed 4 PFXBALW9
0580 1408 Bitstring 1 PFXBALW$ (0)
SAVBK extension: Saveareas in the
SAVBK format *may* have the high halves of
registers stored in the tail end. Bit SAVERG64 in the
savearea header indicates that these fields are valid.
0580 1408 Signed 4 * (4) Reserved for future use
0590 1424 Signed 4 * (4) Reserved for future use
The SAVBK SAVEAARP and the SVGBK SVGAARP fields must be
at the same offset into each control block. The only
available area in both that satisfies this requirement
is, unfortunately, here in the middle of the control
block.
05A0 1440 Address 4 PFXBALOPNR A(who set SVHOPEN)
05A4 1444 Signed 4 * Reserved for IBM use
05A8 1448 Address 4 PFXBALAARP A(AR sidecar) for PFX saveareas
05AC 1452 Bitstring 1 PFXBALIACA Caller actual IAC
05AD 1453 Bitstring 1 PFXBALAMDE Amode of callee at entry.
05AE 1454 Bitstring 1 PFXBALIACR Caller "should be" IAC
05AF 1455 Bitstring 1 PFXBALIACE Callee "should be" IAC
05B0 1456 Signed 4 * (4) Reserved for future use
05C0 1472 Bitstring 64 PFXBALHIRG (0)
05C0 1472 Signed 4 PFXBALH0 High word of zArch general reg 0
05C4 1476 Signed 4 PFXBALH1 High word of zArch general reg 1
05C8 1480 Signed 4 PFXBALH2 High word of zArch general reg 2
05CC 1484 Signed 4 PFXBALH3 High word of zArch general reg 3
05D0 1488 Signed 4 PFXBALH4 High word of zArch general reg 4
05D4 1492 Signed 4 PFXBALH5 High word of zArch general reg 5
05D8 1496 Signed 4 PFXBALH6 High word of zArch general reg 6
05DC 1500 Signed 4 PFXBALH7 High word of zArch general reg 7
05E0 1504 Signed 4 PFXBALH8 High word of zArch general reg 8
05E4 1508 Signed 4 PFXBALH9 High word of zArch general reg 9
05E8 1512 Signed 4 PFXBALH10 High word of zArch general reg 10
05EC 1516 Signed 4 PFXBALH11 High word of zArch general reg 11
05F0 1520 Signed 4 PFXBALH12 High word of zArch general reg 12
05F4 1524 Signed 4 PFXBALH13 High word of zArch general reg 13
05F8 1528 Signed 4 PFXBALH14 High word of zArch general reg 14
05FC 1532 Signed 4 PFXBALH15 High word of zArch general reg 15
05A8 1448 Bitstring 4 * A(AR SIDECAR) FOR PFX SAVEAREA
THIS AREA HAS THE SAME FORMAT AS A SAVEAREA IN HCPSAVBK
0600 1536 Signed 4 PFXPTRFP
0604 1540 Signed 4 PFXPTRBP
0608 1544 Signed 4 *
060C 1548 Signed 4 *
0610 1552 Bitstring 1 PFXPTRSC
0611 1553 Bitstring 1 PFXPTRCL
0612 1554 Bitstring 1 *
0613 1555 Bitstring 1 *
0614 1556 Signed 4 *
0618 1560 Bitstring 232 PFXPTRAREA (0) Register and working storage
0618 1560 Bitstring 64 PFXPTRRG (0) Caller's registers
0618 1560 Signed 4 PFXPTRR0 (0) Caller's saved register 0
0618 1560 Bitstring 1 PFXPTRR0B0 byte 0
0619 1561 Bitstring 1 PFXPTRR0B1 byte 1
061A 1562 Bitstring 1 PFXPTRR0B2 byte 2
061B 1563 Bitstring 1 PFXPTRR0B3 byte 3
061C 1564 Signed 4 PFXPTRR1 (0) Caller's saved register 1
061C 1564 Bitstring 1 PFXPTRR1B0 byte 0
061D 1565 Bitstring 1 PFXPTRR1B1 byte 1
061E 1566 Bitstring 1 PFXPTRR1B2 byte 2
061F 1567 Bitstring 1 PFXPTRR1B3 byte 3
0620 1568 Signed 4 PFXPTRR2 (0) Caller's saved register 2 THE
FOLLOWING BYTE DEFINITIONS OF
SAVER2 ARE FOR TESTING PARAMETERS
PASSED BETWEEN MODULES.
0620 1568 Bitstring 1 PFXPTRR2B0 byte 0
0621 1569 Bitstring 1 PFXPTRR2B1 byte 1
0622 1570 Bitstring 1 PFXPTRR2B2 byte 2
0623 1571 Bitstring 1 PFXPTRR2B3 byte 3
0624 1572 Signed 4 PFXPTRR3 Caller's saved register 3
0628 1576 Signed 4 PFXPTRR4 Caller's saved register 4
062C 1580 Signed 4 PFXPTRR5 Caller's saved register 5
0630 1584 Signed 4 PFXPTRR6 Caller's saved register 6
0634 1588 Signed 4 PFXPTRR7 Caller's saved register 7
0638 1592 Signed 4 PFXPTRR8 Caller's saved register 8
063C 1596 Signed 4 PFXPTRR9 Caller's saved register 9
0640 1600 Signed 4 PFXPTRRA Caller's saved register 10
0644 1604 Signed 4 PFXPTRRB Caller's saved register 11; ALSO
VMDBK ADDRESS OF USER ON WHICH
SAVBK IS SCHEDULED
0648 1608 Bitstring 16 PFXPTRRCF (0) Caller's saved register 12-15
0648 1608 Signed 4 PFXPTRRC Caller's saved register 12
064C 1612 Signed 4 PFXPTRRD Caller's saved register 13; ALSO
PREVIOUS SAVBK ADDRESS ON CALL
0650 1616 Signed 4 PFXPTRRE Caller's saved register 14; ALSO
RETURN ADDRESS ON CALL OR STACKED
SAVBK RETURN
0654 1620 Signed 4 PFXPTRRF Caller's saved register 15; ALSO
GOTO ADDRESS ON SCHEDULED SAVBK
EXECUTION; ALSO REGISTER 15
RETURN CODE ON HCPEXIT OR STACKED
SAVBK RETURN
0658 1624 Bitstring 40 PFXPTRWK (0) Workarea for callee
0658 1624 Signed 4 PFXPTRW0
065C 1628 Signed 4 PFXPTRW1
0660 1632 Signed 4 PFXPTRW2
0664 1636 Signed 4 PFXPTRW3
0668 1640 Signed 4 PFXPTRW4
066C 1644 Signed 4 PFXPTRW5
0670 1648 Signed 4 PFXPTRW6
0674 1652 Signed 4 PFXPTRW7
0678 1656 Signed 4 PFXPTRW8
067C 1660 Signed 4 PFXPTRW9
0680 1664 Bitstring 1 PFXPTRW$ (0)
SAVBK extension: Saveareas in the
SAVBK format *may* have the high halves of
registers stored in the tail end. Bit SAVERG64 in the
savearea header indicates that these fields are valid.
0680 1664 Signed 4 * (4) Reserved for future use
0690 1680 Signed 4 * (4) Reserved for future use
The SAVBK SAVEAARP and the SVGBK SVGAARP fields must be
at the same offset into each control block. The only
available area in both that satisfies this requirement
is, unfortunately, here in the middle of the control
block.
06A0 1696 Address 4 PFXPTROPNR A(who set SVHOPEN)
06A4 1700 Signed 4 * Reserved for IBM use
06A8 1704 Address 4 PFXPTRAARP A(AR sidecar) for PFX saveareas
06AC 1708 Bitstring 1 PFXPTRIACA Caller actual IAC
06AD 1709 Bitstring 1 PFXPTRAMDE Amode of callee at entry.
06AE 1710 Bitstring 1 PFXPTRIACR CALLER "SHOULD BE" IAC
06AF 1711 Bitstring 1 PFXPTRIACE Callee "should be" IAC
06B0 1712 Signed 4 * (4) Reserved for future use
06C0 1728 Bitstring 64 PFXPTRHIRG (0)
06C0 1728 Signed 4 PFXPTRH0 High word of zArch general reg 0
06C4 1732 Signed 4 PFXPTRH1 High word of zArch general reg 1
06C8 1736 Signed 4 PFXPTRH2 High word of zArch general reg 2
06CC 1740 Signed 4 PFXPTRH3 High word of zArch general reg 3
06D0 1744 Signed 4 PFXPTRH4 High word of zArch general reg 4
06D4 1748 Signed 4 PFXPTRH5 High word of zArch general reg 5
06D8 1752 Signed 4 PFXPTRH6 High word of zArch general reg 6
06DC 1756 Signed 4 PFXPTRH7 High word of zArch general reg 7
06E0 1760 Signed 4 PFXPTRH8 High word of zArch general reg 8
06E4 1764 Signed 4 PFXPTRH9 High word of zArch general reg 9
06E8 1768 Signed 4 PFXPTRH10 High word of zArch general reg 10
06EC 1772 Signed 4 PFXPTRH11 High word of zArch general reg 11
06F0 1776 Signed 4 PFXPTRH12 High word of zArch general reg 12
06F4 1780 Signed 4 PFXPTRH13 High word of zArch general reg 13
06F8 1784 Signed 4 PFXPTRH14 High word of zArch general reg 14
06FC 1788 Signed 4 PFXPTRH15 High word of zArch general reg 15
06A8 1704 Bitstring 4 * A(AR SIDECAR) FOR PFX SAVEAREA
THIS AREA HAS THE SAME FORMAT AS A SAVEAREA IN HCPSAVBK
0700 1792 Signed 4 PFXFREFP
0704 1796 Signed 4 PFXFREBP
0708 1800 Signed 4 *
070C 1804 Signed 4 *
0710 1808 Bitstring 1 PFXFRESC
0711 1809 Bitstring 1 PFXFRECL
0712 1810 Bitstring 1 *
0713 1811 Bitstring 1 *
0714 1812 Signed 4 *
0718 1816 Bitstring 232 PFXFREAREA (0) Register and working storage
0718 1816 Bitstring 64 PFXFRERG (0) Caller's registers
0718 1816 Signed 4 PFXFRER0 (0) Caller's saved register 0
0718 1816 Bitstring 1 PFXFRER0B0 byte 0
0719 1817 Bitstring 1 PFXFRER0B1 byte 1
071A 1818 Bitstring 1 PFXFRER0B2 byte 2
071B 1819 Bitstring 1 PFXFRER0B3 byte 3
071C 1820 Signed 4 PFXFRER1 (0) Caller's saved register 1
071C 1820 Bitstring 1 PFXFRER1B0 byte 0
071D 1821 Bitstring 1 PFXFRER1B1 byte 1
071E 1822 Bitstring 1 PFXFRER1B2 byte 2
071F 1823 Bitstring 1 PFXFRER1B3 byte 3
0720 1824 Signed 4 PFXFRER2 (0) Caller's saved register 2 THE
FOLLOWING BYTE DEFINITIONS OF
SAVER2 ARE FOR TESTING PARAMETERS
PASSED BETWEEN MODULES.
0720 1824 Bitstring 1 PFXFRER2B0 byte 0
0721 1825 Bitstring 1 PFXFRER2B1 byte 1
0722 1826 Bitstring 1 PFXFRER2B2 byte 2
0723 1827 Bitstring 1 PFXFRER2B3 byte 3
0724 1828 Signed 4 PFXFRER3 Caller's saved register 3
0728 1832 Signed 4 PFXFRER4 Caller's saved register 4
072C 1836 Signed 4 PFXFRER5 Caller's saved register 5
0730 1840 Signed 4 PFXFRER6 Caller's saved register 6
0734 1844 Signed 4 PFXFRER7 Caller's saved register 7
0738 1848 Signed 4 PFXFRER8 Caller's saved register 8
073C 1852 Signed 4 PFXFRER9 Caller's saved register 9
0740 1856 Signed 4 PFXFRERA Caller's saved register 10
0744 1860 Signed 4 PFXFRERB Caller's saved register 11; ALSO
VMDBK ADDRESS OF USER ON WHICH
SAVBK IS SCHEDULED
0748 1864 Bitstring 16 PFXFRERCF (0) Caller's saved register 12-15
0748 1864 Signed 4 PFXFRERC Caller's saved register 12
074C 1868 Signed 4 PFXFRERD Caller's saved register 13; ALSO
PREVIOUS SAVBK ADDRESS ON CALL
0750 1872 Signed 4 PFXFRERE Caller's saved register 14; ALSO
RETURN ADDRESS ON CALL OR STACKED
SAVBK RETURN
0754 1876 Signed 4 PFXFRERF Caller's saved register 15; ALSO
GOTO ADDRESS ON SCHEDULED SAVBK
EXECUTION; ALSO REGISTER 15
RETURN CODE ON HCPEXIT OR STACKED
SAVBK RETURN
0758 1880 Bitstring 40 PFXFREWK (0) Workarea for callee
0758 1880 Signed 4 PFXFREW0
075C 1884 Signed 4 PFXFREW1
0760 1888 Signed 4 PFXFREW2
0764 1892 Signed 4 PFXFREW3
0768 1896 Signed 4 PFXFREW4
076C 1900 Signed 4 PFXFREW5
0770 1904 Signed 4 PFXFREW6
0774 1908 Signed 4 PFXFREW7
0778 1912 Signed 4 PFXFREW8
077C 1916 Signed 4 PFXFREW9
0780 1920 Bitstring 1 PFXFREW$ (0)
SAVBK extension: Saveareas in the
SAVBK format *may* have the high halves of
registers stored in the tail end. Bit SAVERG64 in the
savearea header indicates that these fields are valid.
0780 1920 Signed 4 * (4) Reserved for future use
0790 1936 Signed 4 * (4) Reserved for future use
The SAVBK SAVEAARP and the SVGBK SVGAARP fields must be
at the same offset into each control block. The only
available area in both that satisfies this requirement
is, unfortunately, here in the middle of the control
block.
07A0 1952 Address 4 PFXFREOPNR A(who set SVHOPEN)
07A4 1956 Signed 4 * Reserved for IBM use
07A8 1960 Address 4 PFXFREAARP A(AR sidecar) for PFX saveareas
07AC 1964 Bitstring 1 PFXFREIACA Caller actual IAC
07AD 1965 Bitstring 1 PFXFREAMDE Amode of callee at entry.
07AE 1966 Bitstring 1 PFXFREIACR Caller "should be" IAC
07AF 1967 Bitstring 1 PFXFREIACE Callee "should be" IAC
07B0 1968 Signed 4 * (4) Reserved for future use
07C0 1984 Bitstring 64 PFXFREHIRG (0)
07C0 1984 Signed 4 PFXFREH0 High word of zArch general reg 0
07C4 1988 Signed 4 PFXFREH1 High word of zArch general reg 1
07C8 1992 Signed 4 PFXFREH2 High word of zArch general reg 2
07CC 1996 Signed 4 PFXFREH3 High word of zArch general reg 3
07D0 2000 Signed 4 PFXFREH4 High word of zArch general reg 4
07D4 2004 Signed 4 PFXFREH5 High word of zArch general reg 5
07D8 2008 Signed 4 PFXFREH6 High word of zArch general reg 6
07DC 2012 Signed 4 PFXFREH7 High word of zArch general reg 7
07E0 2016 Signed 4 PFXFREH8 High word of zArch general reg 8
07E4 2020 Signed 4 PFXFREH9 High word of zArch general reg 9
07E8 2024 Signed 4 PFXFREH10 High word of zArch general reg 10
07EC 2028 Signed 4 PFXFREH11 High word of zArch general reg 11
07F0 2032 Signed 4 PFXFREH12 High word of zArch general reg 12
07F4 2036 Signed 4 PFXFREH13 High word of zArch general reg 13
07F8 2040 Signed 4 PFXFREH14 High word of zArch general reg 14
07FC 2044 Signed 4 PFXFREH15 High word of zArch general reg 15
07A8 1960 Bitstring 4 * A(AR SIDECAR) FOR PFX SAVEAREA
RE-DEFINITION OF PFXIRPSV FOR INDIVIDUAL REGISTERS
0800 2048 Signed 4 PFXIRP12 R12 SAVE AREA
0804 2052 Signed 4 PFXIRP13 R13 SAVE AREA
0808 2056 Signed 4 PFXIRP14 R14 SAVE AREA
080C 2060 Signed 4 PFXIRP15 R15 SAVE AREA
RE-DEFINITION OF PFXLNKSG FOR 64-BIT REGISTERS
0820 2080 Dbl-Word 8 PFXLNKGC R12 SAVE AREA
0828 2088 Dbl-Word 8 PFXLNKGD R13 SAVE AREA
0830 2096 Dbl-Word 8 PFXLNKGE R14 SAVE AREA
0838 2104 Dbl-Word 8 PFXLNKGF R15 SAVE AREA
RE-DEFINITION OF PFXLNKSV FOR INDIVIDUAL REGISTERS
0820 2080 Signed 4 PFXLNK12 R12 SAVE AREA
0824 2084 Signed 4 PFXLNK13 R13 SAVE AREA
0828 2088 Signed 4 PFXLNK14 R14 SAVE AREA
082C 2092 Signed 4 PFXLNK15 R15 SAVE AREA
TIMER WORK REGION
02C0 704 Signed 4 PFXTODHO (0) High half of TOD clock
02C0 704 Signed 8 PFXCVTDA Work area for HCPCVTxx. Some code
also relies on finding a recent
TOD value left behind here. (Such
a value might be from STCK or
STCKF, or a substring from
STCKE.)
02C8 712 Signed 8 PFXPTLBT TOD clock at (actually, before)
last TLB (and ALB) purge (whether
by PTLB & PALB or CSP / CSPG
purging both ALBs and TLBs
globally) on this CPU
02D0 720 Signed 8 PFXTMRUN CPU TIMER AT USER RUN
02D8 728 Signed 8 PFXTMURN CPU TIMER AT USER UN-RUN
02E0 736 Signed 8 PFXTMDSP CPU TIMER AT USER DISPATCH
02E8 744 Signed 8 PFXTMUDS CPU TIMER AT USER UN-DISPATCH
02F0 752 Signed 8 PFXVTDSP VALUE OF VMSVTIME AT USER
DISPATCH
02F8 760 Signed 8 PFXPTLBL TOD Clock at last PTLB on this
CPU (never zeroed, unlike
PFXPTLBT)
Host Control Register Savearea
Although z/Architecture CRs are 8 bytes, in most
cases, CP only uses the rightmost word or 4 bytes,
with zeros in the leftmost word of the CR. CR1,
CR7, and CR13 contain ASCEs, and are exceptions:
ASCEs designate upper level DAT tables (Region
First, Region Second, Region Third, or Segment
Tables) which can reside above 2G and thus may have
non-zero values in the leftmost word.
For CR0, CP never sets the two bits defined in the
leftmost word (CR0.0 and CR0.1).
For CR1,7,13 the ASCEs loaded always point to CP
allocated control blocks that may be above
or below the 2G line. LCTLG and STCTLG
must be used for these CRs.
For CR10,11 CP never sets host PER addresses.
For CR12 the CP trace table is always allocated
in pages below the 2G line.
For CR15 CP never uses the Linkage-Stack facility.
0E80 3712 Bitstring 128 PFXCPCR (0) Host Control Registers
CR0 Control bits and masks
0E80 3712 Signed 8 PFXCPCR0G (0) Control and External Masks
0E80 3712 Signed 4 PFXCPCR0H (0) CR0 high word
0E80 3712 Bitstring 1 * Reserved for IBM use
0E81 3713 Bitstring 1 PFXCR0HB1
0E82 3714 Bitstring 2 * Reserved for IBM use
0E84 3716 Signed 4 PFXCPCR0 (0) Control and External Masks
0E84 3716 Bitstring 1 PFXCR0B0
0E85 3717 Bitstring 1 PFXCR0B1
0E86 3718 Bitstring 1 PFXCR0B2
0E87 3719 Bitstring 1 PFXCR0B3
CR1 Primary Address-Space-Control Element (ASCE)
0E88 3720 Signed 8 PFXCPCR1G (0) Primary ASCE
0E88 3720 Signed 4 PFXCPCR1H CR1 high half (Primary ASCE)
0E8C 3724 Signed 4 PFXCPCR1 (0) Primary ASCE
0E8C 3724 Bitstring 1 PFXCR1B0 NO BITS DEFINED FOR PFXCR1B1
1... .... CR1SSXA X'80' CR1SSXA 370/XA SPACE SWITCH
EVENT MASK
0E8D 3725 Bitstring 1 PFXCR1B1 NO BITS DEFINED FOR PFXCR1B2
0E8E 3726 Bitstring 1 PFXCR1B2 NO BITS DEFINED FOR PFXCR1B3
0E8F 3727 Bitstring 1 PFXCR1B3
CR2 Dispatchable-Unit-Control-Table Origin
0E90 3728 Signed 8 PFXCPCR2G (0) DUCTO
0E90 3728 Signed 4 PFXCPCR2H CR2 high half (DUCTO) @
0E94 3732 Signed 4 PFXCPCR2 (0) NO BITS DEFINED FOR PFXCR2B0
0E94 3732 Bitstring 1 PFXCR2B0 NO BITS DEFINED FOR PFXCR2B1 BY
HCPEQUAT
0E95 3733 Bitstring 1 PFXCR2B1 NO BITS DEFINED FOR PFXCR2B2 BY
HCPEQUAT
0E96 3734 Bitstring 1 PFXCR2B2 NO BITS DEFINED FOR PFXCR2B3 BY
HCPEQUAT
0E97 3735 Bitstring 1 PFXCR2B3
CR3 PSW-Key Mask, Secondary Address-Space-Number (ASN)
0E98 3736 Signed 8 PFXCPCR3G (0) CR3
0E98 3736 Signed 4 PFXCPCR3H CR3 high half (reserved)
0E9C 3740 Signed 4 PFXCPCR3 (0) NO BITS DEFINED FOR PFXCR3B0 BY
HCPEQUAT
0E9C 3740 Bitstring 1 PFXCR3B0 NO BITS DEFINED FOR PFXCR3B1 BY
HCPEQUAT
0E9D 3741 Bitstring 1 PFXCR3B1 NO BITS DEFINED FOR PFXCR3B2 BY
HCPEQUAT
0E9E 3742 Bitstring 1 PFXCR3B2 NO BITS DEFINED FOR PFXCR3B3 BY
HCPEQUAT
0E9F 3743 Bitstring 1 PFXCR3B3
CR4 Authorization Index, Primary Address-Space-Number
0EA0 3744 Signed 8 PFXCPCR4G (0) CR4
0EA0 3744 Signed 4 PFXCPCR4H CR4 high half (reserved)
0EA4 3748 Signed 4 PFXCPCR4 (0) NO BITS DEFINED FOR PFXCR4B0 BY
HCPEQUAT
0EA4 3748 Bitstring 1 PFXCR4B0 NO BITS DEFINED FOR PFXCR4B1 BY
HCPEQUAT
0EA5 3749 Bitstring 1 PFXCR4B1 NO BITS DEFINED FOR PFXCR4B2 BY
HCPEQUAT
0EA6 3750 Bitstring 1 PFXCR4B2 NO BITS DEFINED FOR PFXCR4B3 BY
HCPEQUAT
0EA7 3751 Bitstring 1 PFXCR4B3
CR5 Primary-ASTE origin
0EA8 3752 Signed 8 PFXCPCR5G (0) CR5
0EA8 3752 Signed 4 PFXCPCR5H CR5 high half (reserved)
0EAC 3756 Signed 4 PFXCPCR5 (0) NO BITS DEFINED FOR PFXCR5B0 BY
HCPEQUAT
0EAC 3756 Bitstring 1 PFXCR5B0 NO BITS DEFINED FOR PFXCR5B1 BY
HCPEQUAT
0EAD 3757 Bitstring 1 PFXCR5B1 NO BITS DEFINED FOR PFXCR5B2 BY
HCPEQUAT
0EAE 3758 Bitstring 1 PFXCR5B2 NO BITS DEFINED FOR PFXCR5B3 BY
HCPEQUAT
0EAF 3759 Bitstring 1 PFXCR5B3
CR6 I/O-Interruption Subclass Mask
0EB0 3760 Signed 8 PFXCPCR6G (0) CR6
0EB0 3760 Signed 4 PFXCPCR6H CR6 high half (reserved)
0EB4 3764 Signed 4 PFXCPCR6 (0) I/0 INTERRUPTION SUBCLASS MASKS
0EB4 3764 Bitstring 1 PFXCR6B0
1... .... PFXCPIOI X'80' PFXCPIOI I/O INTERRUPT
SUBCLASS 00 FOR CP-INITIATED I/O
1... .... PFXIOCL0 X'80' PFXIOCL0 FLOATING CHANNEL
INTERRUPT CLASS 0
.1.. .... PFXIOCL1 X'40' PFXIOCL1 FLOATING CHANNEL
INTERRUPT CLASS 1
..1. .... PFXIOCL2 X'20' PFXIOCL2 FLOATING CHANNEL
INTERRUPT CLASS 2
...1 .... PFXIOCL3 X'10' PFXIOCL3 FLOATING CHANNEL
INTERRUPT CLASS 3
.... 1... PFXIOCL4 X'08' PFXIOCL4 FLOATING CHANNEL
INTERRUPT CLASS 4
.... .1.. PFXIOCL5 X'04' PFXIOCL5 FLOATING CHANNEL
INTERRUPT CLASS 5
.... ..1. PFXIOCL6 X'02' PFXIOCL6 FLOATING CHANNEL
INTERRUPT CLASS 6
.... ...1 PFXIOCL7 X'01' PFXIOCL7 FLOATING CHANNEL
INTERRUPT CLASS 7
...1 11.1 PFXDRFPT X'1D' PFXDRFPT INTERRUPTION
SUBCLASSES DEDICATED FOR LEVEL 2
I/O PASS THRU'S USE.(3,4,5,7) NO
BITS DEFINED FOR PFXCR6B1 BY
HCPEQUAT
0EB5 3765 Bitstring 1 PFXCR6B1 NO BITS DEFINED FOR PFXCR6B2 BY
HCPEQUAT
0EB6 3766 Bitstring 1 PFXCR6B2 NO BITS DEFINED FOR PFXCR6B3 BY
HCPEQUAT
0EB7 3767 Bitstring 1 PFXCR6B3
CR7 Secondary Address-Space-Control Element (ASCE)
0EB8 3768 Signed 8 PFXCPCR7G (0) CR7
0EB8 3768 Signed 4 PFXCPCR7H CR7 high half (Secondary ASCE)
0EBC 3772 Signed 4 PFXCPCR7 (0) NO BITS DEFINED FOR PFXCR7B0 BY
HCPEQUAT
0EBC 3772 Bitstring 1 PFXCR7B0 NO BITS DEFINED FOR PFXCR7B1 BY
HCPEQUAT
0EBD 3773 Bitstring 1 PFXCR7B1 NO BITS DEFINED FOR PFXCR7B2 BY
HCPEQUAT
0EBE 3774 Bitstring 1 PFXCR7B2 NO BITS DEFINED FOR PFXCR7B3 BY
HCPEQUAT
0EBF 3775 Bitstring 1 PFXCR7B3
CR8 Extended Authorization Index, Monitor Masks
0EC0 3776 Signed 8 PFXCPCR8G (0) CR8
0EC0 3776 Signed 4 PFXCPCR8H CR8 high half (reserved)
0EC4 3780 Signed 4 PFXCPCR8 (0) MONITOR CALL ENABLE MASKS
NO BITS DEFINED FOR PFXCR8B0 BY HCPEQUAT
0EC4 3780 Bitstring 1 PFXCR8B0 NO BITS DEFINED FOR PFXCR8B1 BY
HCPEQUAT
0EC5 3781 Bitstring 1 PFXCR8B1 NO BITS DEFINED FOR PFXCR8B2 BY
HCPEQUAT
0EC6 3782 Bitstring 1 PFXCR8B2 NO BITS DEFINED FOR PFXCR8B3 BY
HCPEQUAT
0EC7 3783 Bitstring 1 PFXCR8B3
CR9 PER Control
0EC8 3784 Signed 8 PFXCPCR9G (0) CR9
0EC8 3784 Signed 4 PFXCPCR9H CR9 high half (reserved)
0ECC 3788 Signed 4 PFXCPCR9 (0) PER CONTROL
0ECC 3788 Bitstring 1 PFXCR9B0 NO BITS DEFINED FOR PFXCR9B1 BY
HCPEQUAT
0ECD 3789 Bitstring 1 PFXCR9B1
0ECE 3790 Bitstring 1 PFXCR9B2
0ECF 3791 Bitstring 1 PFXCR9B3
CR10 PER Address Range - Starting Address
0ED0 3792 Signed 8 PFXCPCRAG (0) CR10
0ED0 3792 Signed 4 PFXCPCRAH CR10 high half (PER range)
0ED4 3796 Signed 4 PFXCPCRA PER ADDRESS RANGE
CR11 PER Address Range - Ending Address
0ED8 3800 Signed 8 PFXCPCRBG (0) CR11
0ED8 3800 Signed 4 PFXCPCRBH CR11 high half (PER range)
0EDC 3804 Signed 4 PFXCPCRB PER ADDRESS RANGE
CR12 Trace Controls
0EE0 3808 Signed 8 PFXCPCRCG (0) CR12
0EE0 3808 Signed 4 PFXCPCRCH CR12 high half (Trace controls)
0EE4 3812 Signed 4 PFXCPCRC (0)
0EE4 3812 Bitstring 1 PFXCRCB0 NO BITS DEFINED FOR PFXCRCB1 BY
HCPEQUAT
1... .... CRCBRCTL X'80' CRCBRCTL BRANCH TRACE
CONTROL BIT. WHEN ON, BALR, BASR,
BASSM, BAKR AND BSG INST MAY BE
TRACED BY THE HARDWARE. Note that
for zArch, this bit is moved to
GCRC0.0 of a 64-bit CRC with a
label of CRCBTCTL.
0EE5 3813 Bitstring 1 PFXCRCB1 NO BITS DEFINED FOR PFXCRCB2 BY
HCPEQUAT
0EE6 3814 Bitstring 1 PFXCRCB2
0EE7 3815 Bitstring 1 PFXCRCB3
CR13 Home Address-Space-Control Element
0EE8 3816 Signed 8 PFXCPCRDG (0) CR13
0EE8 3816 Signed 4 PFXCPCRDH CR13 high half (Home ASCE)
0EEC 3820 Signed 4 PFXCPCRD (0) NO BITS DEFINED FOR PFXCRDB0 BY
HCPEQUAT CRDB0
0EEC 3820 Bitstring 1 PFXCRDB0 NO BITS DEFINED FOR PFXCRDB1 BY
HCPEQUAT CRDB1
0EED 3821 Bitstring 1 PFXCRDB1 NO BITS DEFINED FOR PFXCRDB2 BY
HCPEQUAT CRDB2
0EEE 3822 Bitstring 1 PFXCRDB2 NO BITS DEFINED FOR PFXCRDB3 BY
HCPEQUAT CRDB3
0EEF 3823 Bitstring 1 PFXCRDB3
CR14 Machine Check Masks, TOD clock control,
ASN Translation Control
0EF0 3824 Signed 8 PFXCPCREG (0) CR14
0EF0 3824 Signed 4 PFXCPCREH CR14 high half (reserved)
0EF4 3828 Signed 4 PFXCPCRE (0) MACHINE CHECK CONTROL MASK
0EF4 3828 Bitstring 1 PFXCREB0
0EF5 3829 Bitstring 1 PFXCREB1 NO BITS DEFINED FOR PFXCREB2 BY
HCPEQUAT
0EF6 3830 Bitstring 1 PFXCREB2 NO BITS DEFINED FOR PFXCREB3 BY
HCPEQUAT
0EF7 3831 Bitstring 1 PFXCREB3
CR15 Linkage-Stack-Entry Address
0EF8 3832 Signed 8 PFXCPCRFG (0) CR15
0EF8 3832 Signed 4 PFXCPCRFH CR15 high half (Linkage Stack)
0EFC 3836 Signed 4 PFXCPCRF (0) NO BITS DEFINED FOR PFXCRFB0 BY
HCPEQUAT
0EFC 3836 Bitstring 1 PFXCRFB0 NO BITS DEFINED FOR PFXCRFB1 BY
HCPEQUAT
0EFD 3837 Bitstring 1 PFXCRFB1 NO BITS DEFINED FOR PFXCRFB2 BY
HCPEQUAT
0EFE 3838 Bitstring 1 PFXCRFB2 NO BITS DEFINED FOR PFXCRFB3 BY
HCPEQUAT
0EFF 3839 Bitstring 1 PFXCRFB3
THE FOLLOWING INITIAL VALUES FOR THE CONTROL REGS
ARE FOR USE BY SYSTEM INITIALIZATION PRIOR TO
SETTING THE ACTUAL RUNNING VALUE.
PFXCPCR6,PFXCPCR7,PFXCPCR8,PFXCPCR9,PFXCPCRA,PFXCPCRB,
PFXCPCRC,PFXCPCRD,PFXCPCRE,PFXCPCRF
0E80 3712 Address 4 * (0) R5,PFXCPCR6,PFXCPCR7,PFXCPCR8,PFX
CPCR9,PFXCPCRA,PFXCPCRB
,PFXCPCRC,PFXCPCRD,PFXCPCRE,PFXCP
CRF) Force a cross reference
PFXCPCR5H,PFXCPCR6H,PFXCPCR7H,PFX
CPCR8H,PFXCPCR9H,
PFXCPCRAH,PFXCPCRBH,PFXCPCRCH,PFX
CPCRDH,PFXCPCREH, PFXCPCRFH
0E80 3712 Address 4 * (0) FXCPCR5H,PFXCPCR6H,PFXCPCR7H,PFXC
PCR8H,PFXCPCR9H,PFXCPCR
AH,PFXCPCRBH,PFXCPCRCH,PFXCPCRDH,
PFXCPCREH,PFXCPCRFH) Force a
cross reference
PFXCPCR5G,PFXCPCR6G,PFXCPCR7G,PFX
CPCR8G,PFXCPCR9G,
PFXCPCRAG,PFXCPCRBG,PFXCPCRCG,PFX
CPCRDG,PFXCPCREG, PFXCPCRFG
0E80 3712 Address 4 * (0) FXCPCR5G,PFXCPCR6G,PFXCPCR7G,PFXC
PCR8G,PFXCPCR9G,PFXCPCR
AG,PFXCPCRBG,PFXCPCRCG,PFXCPCRDG,
PFXCPCREG,PFXCPCRFG) Force a
cross reference
0E80 3712 Address 4 * (0) Force a cross reference
0E80 3712 Signed 4 * CR0 High half
0E84 3716 Bitstring 4 * CR0 Control, external masks
0E88 3720 Signed 4 * CR1 Primary-space ASCE
0E90 3728 Signed 4 * CR2 DUCT Origin
0E98 3736 Signed 4 * CR3 PSW-Key Mask, SASN
0EA0 3744 Signed 4 * CR4 Auth. Index, PASN
0EA8 3752 Signed 4 * CR5 Primary ASTE origin
0EB0 3760 Signed 4 * CR6 I/O Int. Subclass Masks
0EB8 3768 Signed 4 * CR7 Secondary-space ASCE
0EC0 3776 Signed 4 * CR8 Monitor Call Masks
0EC8 3784 Signed 4 * CR9 PER Control
0ED0 3792 Signed 4 * CR10 PER Address Range - start
0ED8 3800 Signed 4 * CR11 PER Address Range - end
0EE0 3808 Signed 4 * CR12 Trace Controls
0EE8 3816 Signed 4 * CR13 Home-space ASCE
0EF0 3824 Signed 4 * CR14 Machine check subclasses
0EF8 3832 Signed 4 * CR15 Linkage-Stack-Entry Address
SYSTEM MAINTENANCE SERVICE CODE IDENTIFIER
0900 2304 Character 16 PFXFEIBM 5741-A09 '
THIS SAVEAREA IS REQUIRED BY HCPPRGIN (PROGRAM
INTERRUPT FLIH) TO AVOID DESTROYING THE CONTENTS
OF PFXIRPSV IN THE CASE OF HCPEXT GETTING A TRACE
PROGRAM INTERRUPT WHILE TRYING TO TRACE AN
EXTERNAL INTERRUPT. THE CONTENTS OF THIS SAVEAREA
WILL BE PLACED IN PFXIRPSV IF IT IS DETERMINED
THAT THE PROGRAM INTERRUPT WAS NOT A TRACE
PROGRAM INTERRUPT.
This area is reserved for the time when HCPPRG
becomes LongReg.
0910 2320 Signed 8 * (16) Reserved for HCPPRG
0990 2448 Signed 4 * Reserved for IBM use
0994 2452 Address 4 PFXTTATB Table of trace entry codes
0998 2456 Address 4 PFXSYS SYSTEM COMMON AREA
099C 2460 Address 4 PFXSXLEN Shared-exclusive spinlock SXLEN
array origin address. Updates
serialized by HCPRCCVA (Vary
Proc).
09A0 2464 Address 4 PFXSYSVM SYSTEM VMDBLOCK
09A4 2468 Address 4 PFXSYSMP Address of SYSTEMMP VMDBK
09A8 2472 Signed 4 * Reserved for IBM use
09AC 2476 Signed 4 * Reserved for IBM use
09B0 2480 Signed 4 * Reserved for IBM use
09B4 2484 Signed 4 * Reserved for IBM use
09B8 2488 Signed 4 * Reserved for IBM use
09BC 2492 Address 4 PFXPAGCP End of the CP Nucleus (and
RAMDISK if present.)
09C0 2496 Signed 4 * Reserved for IBM use
09C4 2500 Address 4 PFXLUSER PRIOR RUNNING USER
09C8 2504 Address 4 PFXPRFIX PREFIX VALUE FOR THIS CPU
09CC 2508 Address 4 PFXNXTPF CYCLIC POINTER TO NEXT PREFIX
AREA If there is only one
processor (in other words no
other prefix areas) then it
points to its own prefix area.
09D0 2512 Signed 4 PFXABEND (0) CP ABNORMAL TERMINATION CODE
09D0 2512 Signed 4 PFXTRMCD (0) Machine check termination code
09D0 2512 Bitstring 3 PFXABENM CP ABEND MODULE ID
09D3 2515 Bitstring 1 PFXABENN CP ABEND DETAIL CODE
09D4 2516 Address 4 PFXSXAST Host real address of ASTE for...
system-execution address space.
09D8 2520 Address 4 PFXSTDBK SYSTEM TERMINATION DUMP BLOCK
ADDRESS
09DC 2524 Address 4 PFXMCHA MACHINE CHECK WORK AREA
09E0 2528 Address 4 PFXMCVBK THIS CPU'S PERMANENT MCVBK. IF
BLOCK IS NON-0, A DAMAGE INCIDENT
IS IN PROGRESS.
09E4 2532 Signed 4 PFXINST1 RESERVED FOR INSTALLATION USE
09E8 2536 Signed 4 PFXINST2 RESERVED FOR INSTALLATION USE
09EC 2540 Signed 4 PFXINST3 RESERVED FOR INSTALLATION USE
09F0 2544 Signed 4 PFXINST4 RESERVED FOR INSTALLATION USE
COMMONLY USED CONSTANTS
WARNING: THIS AREA IS OVERLAID BELOW TO PROVIDE
HALFWORD AND BYTE CONSTANTS. CHANGES TO THIS
AREA MUST TAKE THE HALFWORDS AND BYTES INTO
CONSIDERATION.
0A00 2560 Dbl-Word 8 PFXZEROS (8) 64 bytes of binary zeroes
0A40 2624 Bitstring 8 PFXBLANK
0A48 2632 Bitstring 8 PFXFFS
00PFXFFS PFX16Em1 00008 PFXFFs,L'PFXFFs,C'F' /*
16E-1 */
00PFXFFS PFX0 00004 PFXZEROS,4
0A50 2640 Signed 4 PFX1
0A54 2644 Signed 4 PFX2
0A58 2648 Signed 4 PFX3
0A5C 2652 Signed 4 PFX4
0A60 2656 Signed 4 PFX5
0A64 2660 Signed 4 PFX6
0A68 2664 Signed 4 PFX7
0A6C 2668 Signed 4 PFX8
0A70 2672 Signed 4 PFX9
0A74 2676 Signed 4 PFX10
0A78 2680 Signed 4 PFX15 ALSO = X'0000000F'
0A7C 2684 Signed 4 PFX16
0A80 2688 Signed 4 PFX17
0A84 2692 Signed 4 PFX20
0A88 2696 Signed 4 PFX24
0A8C 2700 Signed 4 PFX60 ALSO = X'0000003C'
0A90 2704 Signed 4 PFX240 ALSO = X'000000F0' = C'0'
0A94 2708 Signed 4 PFX255 ALSO = X'000000FF'
0A98 2712 Signed 4 PFX256 ALSO = X'00000100'
0A9C 2716 Signed 4 PFX512 ALSO = X'00000200'
0AA0 2720 Signed 4 PFX2047 ALSO = X'000007FF'
0AA4 2724 Signed 4 PFX2048 ALSO = X'00000800'
0AA8 2728 Signed 4 PFX4095 ALSO = X'00000FFF'
0AAC 2732 Signed 4 PFX4096 ALSO = X'00001000'
0PFX4096 PFXPG2AD PFX4096 PFXPG2AD Address of the
2nd page of the PSA The above is
a temporary proposal for how to
address page 2 of the prefix
area. Directly loading PFX4096
seems wrong.
0AB0 2736 Bitstring 8 PFX24MSK (0) 24-bit address mask
0AB0 2736 Bitstring 4 PFX24HSK . . . 1st half of big mask
0AB4 2740 Bitstring 4 PFX00FFS . . . 2nd half (also small mask)
0AB8 2744 Bitstring 8 PFX2GM1 (0) 2G-1 as unsigned Fixed 64
0AB8 2744 Bitstring 8 PFX31MSK (0) 31-bit address mask
0AB8 2744 Bitstring 4 PFX31HSK . . . 1st half of big mask
0ABC 2748 Bitstring 4 PFX7FFFS . . . 2nd half (also small mask)
. . . also x'7FFFFFFF' in 4 bytes
0AC0 2752 Bitstring 4 PFXHALF ALSO = F'65535' (64K-1)
0AC4 2756 Bitstring 4 PFXPGNUM
PFXPGNUM PFX7F000 PFXPGNUM PFX7F000 XL4'7FFFF000'
PFXPGNUM PFX2GM4K PFXPGNUM PFX2GM4K XL4'2G-4K'
0AC8 2760 Bitstring 4 PFXHLFPG
0ACC 2764 Bitstring 4 PFXSTEMK MASK TO ISOLATE SEGTABLE ENTRY
0AD0 2768 Bitstring 8 PFX2G (0) 2G as unsigned Fixed 64
0AD0 2768 Bitstring 4 PFX2GHI 1st half of 64 bit value
0AD4 2772 Bitstring 4 PFX8000S 2nd half (also 32 bit value)
0AD8 2776 Signed 4 * Reserved for IBM use
0ADC 2780 Bitstring 4 PFXNOADD
0AE0 2784 Signed 4 PFX8192 ALSO = X'00002000'
0PFX8192 PFX8K PFX8192 PFX8K
0AE4 2788 Bitstring 4 PFX7FFE0 Mask to isolate 8K-aligned
address
0AE8 2792 Dbl-Word 8 * (0)
0AE8 2792 Address 8 PFXRXMSK (0)
0AF0 2800 Address 8 PFXGPFRA (0)
00000AF0 PFXGSTOM PFXGPFRA Isolate STO
00000AF0 PFXGRTOM PFXGPFRA Isolate Region Origin
0AF8 2808 Signed 8 * (0)
0AF8 2808 Character 8 PFXFREYE Free Storage trail
pseudo-constant (first word may
be overlaid with FSCBK address
for free storage limit detection,
but is later restored)
COMMONLY USED HALF WORD CONSTANTS
THIS AREA OVERLAYS THE FULL-WORD CONSTANTS
WITH OFFSET +2 FROM THE FULL-WORD FORM.
0A00 2560 Dbl-Word 8 * (8)
0A40 2624 Bitstring 8 *
0A48 2632 Bitstring 8 *
0A50 2640 Signed 2 PFXH0
0A52 2642 Signed 2 PFXH1
0A54 2644 Signed 2 *
0A56 2646 Signed 2 PFXH2
0A58 2648 Signed 2 *
0A5A 2650 Signed 2 PFXH3
0A5C 2652 Signed 2 *
0A5E 2654 Signed 2 PFXH4
0A60 2656 Signed 2 *
0A62 2658 Signed 2 PFXH5
0A64 2660 Signed 2 *
0A66 2662 Signed 2 PFXH6
0A68 2664 Signed 2 *
0A6A 2666 Signed 2 PFXH7
0A6C 2668 Signed 2 *
0A6E 2670 Signed 2 PFXH8
0A70 2672 Signed 2 *
0A72 2674 Signed 2 PFXH9
0A74 2676 Signed 2 *
0A76 2678 Signed 2 PFXH10
0A78 2680 Signed 2 *
0A7A 2682 Signed 2 PFXH15
0A7C 2684 Signed 2 *
0A7E 2686 Signed 2 PFXH16
0A80 2688 Signed 2 *
0A82 2690 Signed 2 PFXH17
0A84 2692 Signed 2 *
0A86 2694 Signed 2 PFXH20
0A88 2696 Signed 2 *
0A8A 2698 Signed 2 PFXH24
0A8C 2700 Signed 2 *
0A8E 2702 Signed 2 PFXH60
0A90 2704 Signed 2 *
0A92 2706 Signed 2 PFXH240
0A94 2708 Signed 2 *
0A96 2710 Signed 2 PFXH255
0A98 2712 Signed 2 *
0A9A 2714 Signed 2 PFXH256
0A9C 2716 Signed 2 *
0A9E 2718 Signed 2 PFXH512
0AA0 2720 Signed 2 *
0AA2 2722 Signed 2 PFXH2047
0AA4 2724 Signed 2 *
0AA6 2726 Signed 2 PFXH2048
0AA8 2728 Signed 2 *
0AAA 2730 Signed 2 PFXH4095
0AAC 2732 Signed 2 *
0AAE 2734 Signed 2 PFXH4096
0AE0 2784 Signed 2 *
0AE2 2786 Signed 2 PFXH8192
COMMONLY USED ONE-BYTE WORD CONSTANTS
THIS AREA OVERLAYS THE FULL-WORD CONSTANTS
WITH OFFSET +3 FROM THE FULL-WORD FORM.
0A00 2560 Dbl-Word 8 * (8)
0A40 2624 Bitstring 8 *
0A48 2632 Bitstring 8 *
0A50 2640 Address 1 PFXB0
0A51 2641 Bitstring 2 *
0A53 2643 Address 1 PFXB1
0A54 2644 Bitstring 3 *
0A57 2647 Address 1 PFXB2
0A58 2648 Bitstring 3 *
0A5B 2651 Address 1 PFXB3
0A5C 2652 Bitstring 3 *
0A5F 2655 Address 1 PFXB4
0A60 2656 Bitstring 3 *
0A63 2659 Address 1 PFXB5
0A64 2660 Bitstring 3 *
0A67 2663 Address 1 PFXB6
0A68 2664 Bitstring 3 *
0A6B 2667 Address 1 PFXB7
0A6C 2668 Bitstring 3 *
0A6F 2671 Address 1 PFXB8
0A70 2672 Bitstring 3 *
0A73 2675 Address 1 PFXB9
0A74 2676 Bitstring 3 *
0A77 2679 Address 1 PFXB10
0A78 2680 Bitstring 3 *
0A7B 2683 Address 1 PFXB15
0A7C 2684 Bitstring 3 *
0A7F 2687 Address 1 PFXB16
0A80 2688 Bitstring 3 *
0A83 2691 Address 1 PFXB17
0A84 2692 Bitstring 3 *
0A87 2695 Address 1 PFXB20
0A88 2696 Bitstring 3 *
0A8B 2699 Address 1 PFXB24
0A8C 2700 Bitstring 3 *
0A8F 2703 Address 1 PFXB60
0A90 2704 Bitstring 3 *
0A93 2707 Address 1 PFXB240 (0)
0A93 2707 Character 1 PFXCHR0
0A94 2708 Bitstring 3 *
0A97 2711 Address 1 PFXB255
0B00 2816 Bitstring 1 PFXSMPFL CPUMF Sampler fast path flags
1... .... PFXSPART X'80' PFXSPART LCPU is
participating in sampling
.1.. .... PFXSGST X'40' PFXSGST Sampling during
guest execution indicator
0B01 2817 Bitstring 1 PFXATTRB Attributes from ICRBK+ICLBK
0B02 2818 Bitstring 1 PFXVCNFG Virtual mode
1... .... PFXVVMXA X'80' PFXVVMXA Running 2nd level
under VM
.1.. .... PFXVLPAR X'40' PFXVLPAR Running in logical
partition
...1 .... PFXVVECT X'10' PFXVVECT Vector Facility
installed. This flag indicates
that host STFLE.129 is on and the
vector register size is 2DW,
which is the only VR size
supported by CP.
.... 1... PFXVBREN X'08' PFXVBREN The BEAR
Enhancement Facility is installed
to the host.
.... ..1. PFXVDG9C X'02' PFXVDG9C Diagnose x'9C' is
installed
.... ...1 PFXVNALC X'01' PFXVNALC
Address-limit-facility not
installed
0B03 2819 Address 1 PFXPREMT CPU PREEMPTION FLAG
000000FF PFXPRERQ 255 PFXPRERQ CPU PREEMPTION IS
REQUESTED
00000000 PFXPREMF 000 PFXPREMF CPU PREEMPTION HAS
BEEN SATISFIED
0B04 2820 Address 4 PFXDSVBK Address of this CPU's dispatch
vector
0B08 2824 Dbl-Word 8 PFXCPUID (0) CPU IDENTIFICATION FIELD
0B08 2824 Bitstring 1 PFXIDVER CPU MODEL VERSION CODE
000000FF CPUIDVM X'FF' CPUIDVM VIRTUAL MACHINE
VERSION CODE
0B09 2825 Bitstring 3 PFXIDSER CPU SERIAL NUMBER - HEXADECIMAL
0B0C 2828 Bitstring 2 PFXIDMDL CPU MODEL NUMBER - HEXADECIMAL
0B0E 2830 Signed 2 * RESERVED FOR FUTURE IBM USE.
0B10 2832 Dbl-Word 8 PFXRNPSW PSW FOR LAST RUN USER
0B18 2840 Dbl-Word 8 PFXDSPRI DISPATCH PRIORITY OF DISPATCHED
VMDBK
0B20 2848 Signed 4 PFXUDED VMDBK TO WHICH THIS CPU IS
DEDICATED (ZERO = NOT A DEDICATED
FIELD)
0B24 2852 Signed 4 PFXIORET RETURN LINKAGE FOR I/O
0B28 2856 Signed 8 PFXLPPUV Doubleword used as the operand of
the LPP instruction by the
dispatcher. The dispatched user's
VMDBK address is in the second
word of this field.
0B28 2856 Signed 4 * Zeroes (first half of LPP
operand)
0B2C 2860 Address 4 PFXRNUSR LAST RUN USER (2nd half of LPP
operand)
0B30 2864 Signed 2 PFXZNNUM HOST ZONE NUMBER
0B32 2866 Bitstring 1 PFXZNMSK HOST ZONE MASK
PFXCPIMG is set very early during system initialization.
It represents the compiled image of the system.
0B33 2867 Bitstring 1 PFXCPIMG Image of CP Executing
.1.. .... PFXCPME X'40' PFXCPME This is the
z/Architecture version
0B34 2868 Signed 4 PFXAZMWD (0) Alert Zone Mask word. This
mapping is used for
compare-and-swap operations.
0B34 2868 Bitstring 1 PFXAZM Alert Zone Mask. This mask
contains a one for each zone
which must be alerted for by this
processor. Serialized by
compare-and-swap.
0B35 2869 Bitstring 3 * Rest of PFXAZMWD
0B38 2872 Signed 4 PFXFLAGS (0) STATUS FLAGS
0B38 2872 Address 1 PFXHSTAT HOST CP RUNNING STATUS
1... .... PFXHWAIT X'80' PFXHWAIT HOST CP IN WAIT
STATE
.1.. .... PFXHRUN X'40' PFXHRUN DISPATCHED USER HAS
BEEN PUT IN THE SIE, OR EXITED
FROM SIE BUT NOT YET 'UN-RUN'.
THE HOST GPR'S AND FPR'S CONTAIN
GUEST DATA, AND THE CPU TIMER IS
TRACKING EMULATION-MODE TIME.
..1. .... PFXHSYS X'20' PFXHSYS HOST CP EXECUTING
ON BEHALF OF SYSTEM
...1 .... PFXHUSER X'10' PFXHUSER HOST CP EXECUTING
ON BEHALF OF USER (PFXHRUN AND/OR
PFXHSYS MAY ALSO BE INDICATED
WITH PFXHUSER)
.... 1... PFXHABEN X'08' PFXHABEN HOST CP ABEND
MACRO HAS BEEN ISSUED
.... .1.. PFXHSIE X'04' PFXHSIE SIE IS RUNNING ON
THIS CPU. (FLAG IS SET JUST
BEFORE START, UNSET JUST AFTER
EXIT.)
.... ..1. PFXHRUNX X'02' PFXHRUNX DISPATCHED USER IS
IN THE 'RUN' STATE, WITH THE
POSSIBLE EXCEPTION OF HOST GPR'S,
WHOSE STATE IS INDICATED SOLELY
BY PFXHRUN.
0B39 2873 Bitstring 1 PFXTNDLK SYSTEM SPECIAL STATES FLAGS
1... .... PFXPWROF X'80' PFXPWROF SHUTDOWN POWEROFF
was issued, and now the IPL
should be done WARM
automatically, with no OPERATOR
intervention. This is set during
IPL based on info contained in
HCPCKPBK (Checkpoint)
.1.. .... PFXHINIT X'40' PFXHINIT CONTROL PROGRAM IS
INITIALIZING
..1. .... PFXSFIPL X'20' PFXSFIPL INITIALIZATION IS
DUE TO SOFTWARE IPL This could be
a bounce or a reIPL of the same
nucleus
...1 .... PFXREIPL X'10' PFXREIPL Initialization is
due to software IPL
.... 1... PFXNOCKP X'08' PFXNOCKP Checkpoint
cylinders were not initialized
.... .1.. PFXTINIT X'04' PFXTINIT TIMER HAS BEEN
INITIALIZED
.... ..1. PFXTRPON X'02' PFXTRPON FREE STORAGE TRAP
IN EFFECT
.... ...1 PFXNULOD X'01' PFXNULOD We needed a new
copy of HCPLOD when we bounced
(or SHUTDOWN REIPL same nucleus)
0B3A 2874 Bitstring 1 PFXRCVFG CPU RECOVERY CONTROL FLAGS
1... .... PFXMALFW X'80' PFXMALFW SPIN LOCK
MALFUNCTION ALERT WINDOW IS IN
PROGRESS
.1.. .... PFXHDLAY X'40' PFXHDLAY PREFIX PAGE IS
AWAITING DE-ALLOCATION
..1. .... PFXRLPST X'20' PFXRLPST Releasing
additional Prefix page STorage at
VARY OFF time
0B3B 2875 Bitstring 1 PFXCPUTY CPU Type of this CPU
0B3C 2876 Bitstring 3 PFXDSPWK (0) Dispatcher work controls
0B3C 2876 Bitstring 1 PFXRCVWK CPU RECOVERY TYPE WORK CONTROLS
.1.. .... PFXMALFP X'40' PFXMALFP MALFUNCTION ALERT
WORK IS PENDING
..1. .... PFXEMSWK X'20' PFXEMSWK EMERGENCY SIGNAL
WORK IS PENDING
...1 .... PFXMCHWK X'10' PFXMCHWK MACHINE CHECK
RECOVERY WORK PENDING
.... .1.. PFXUNPWK X'04' PFXUNPWK UNPARK WORK
PENDING
.... ...1 PFXPRLWK X'01' PFXPRLWK Work pending to
process the page- fault
"processed list" (NOTE: code in
HCPDSP depends on value X'01' for
this)
0B3D 2877 Bitstring 1 PFXTSKST Task state of current task
1... .... PFXDWMCO X'80' PFXDWMCO Dispatched work
can run on Master CPU only.
0B3E 2878 Bitstring 1 PFXAVLwk Various Available List controls.
Serialized by processor local
references only.
.... .1.. PFXCLALtrm X'04' CLAL trim requested
.... ..1. PFXULALtrm X'02' ULAL trim requested
.... ...1 PFXCGALtrm X'01' CGAL trim requested
0B3F 2879 Bitstring 1 PFXEMODE Execution mode flags
1... .... PFXDATON X'80' PFXDATON Run with Dynamic
Address Translation
0B40 2880 Bitstring 1 PFXSVMSK Field used to temporarily save
the program mask. Located in a
cache line frequently ref'd by
HCPDSP and HCPRUN
0B41 2881 Bitstring 1 PFXPNDTK Pending CPU specific tasks,
serialized by compare-and-swap to
allow reach across scheduling of
these tasks
1... .... PFXFOBTR X'80' PFXFOBTR This CPU has been
requested to trim its FOB list
(PFXAFOBL)
.1.. .... PFXNDMRL X'40' PFXNDMRL This CPU has been
requested to reclaim NDMBKs from
it's local recycle queue.
..1. .... PFXMTCTR X'20' PFXMTCTR This CPU has been
requested to extract MT CPUMF
counters.
0B42 2882 Bitstring 1 PFXPKFFL Used to indicate which required
management task needs to be run
for a parked processor. It is
serialized by the Vary Processor
Lock (HCPRCCVA).
000000FF PFXPKINI X'FF' PFXPKINI Initial value when
a CPU is parked
00000001 PFXTTIAE X'01' PFXTTIAE Call HCPTTIAE for
a parked CPU
00000002 PFXUPCR8 X'02' PFXUPCR8 Update CR8 for
Monitor for a parked CPU
00000003 PFXCCFET X'03' PFXCCFET Call HCPCCFET for
a parked CPU
00000004 PFXCCFED X'04' PFXCCFED Call HCPCCFED for
a parked CPU
00000005 PFXCCFCC X'05' PFXCCFCC Call HCPCCFCC for
a parked CPU
00000006 PFXMTCCE X'06' PFXMTCCE Call HCPMTCCE for
a parked CPU
00000007 PFXPROEN X'07' PFXPROEN Call HCPMTFPR for
a parked CPU to turn PFXPROEX oN.
00000008 PFXPROEF X'08' PFXPROEF Call HCPMTFPR for
a parked CPU to turn PFXPROEX
oFf.
00000009 PFXRFIP3 X'09' PFXRFIP3 Call HCPRFIP3 for
a parked CPU
0000000A PFXSMPLE X'0A' PFXSMPLE Call HCPSMPLE for
a parked CPU
0000000A PFXPKMAX PFXSMPLE PFXPKMAX Maximum value
for PFXPKFFL. PFXPROFL is used
for the prorated core time
calculation. The prorated core
time is only calculated when
Multithreading is enabled. Also
when there is only one activated
thread in a core, the prorated
core time will be same as the raw
time.
0B43 2883 Bitstring 1 PFXPROFL Prorated core time calculation
flag
.... .... PFXPRONO X'00' PFXPRONO Prorated core time
is not calculated
.... ...1 PFXPROUP X'01' PFXPROUP Update prorated
core time fields. Set when MT is
enabled. When this bit is off,
the remaining bits in this byte
are also off.
.... ..1. PFXPROEX X'02' PFXPROEX Extract MT
counters for prorated core time
calculation. Set when MT is
enabled and the processor runs on
a multi- threaded core. When this
bit is off, both PFXPREER and
PFXPRMVI are also off.
.... .1.. PFXPREER X'04' PFXPREER MT counters
extraction error and prorated
core time = raw time. When this
bit is on, both PFXPROUP and
PFXPROEX are also on.
.... 1... PFXPRMVI X'08' PFXPRMVI MT counters
monotonicity violation and
prorated core time = raw time.
When this bit is on, both
PFXPROUP and PFXPROEX are also
on.
...1 .... PFXPRNSE X'10' PFXPRNSE No starting
counter values extracted.
Prorated core time = raw time.
When this bit is on, both
PFXPROUP and PFXPROEX are also
on. This bit is set when PFXPROEX
is turned on in case it was done
during a dispatch.
0B44 2884 Signed 2 PFXCPUAD 'STAP' PROCESSOR ADDRESS Note
that we initialize to FF's so
field will be considered
uninitialized when it is GEN'd
into HCPPFX, since we don't know
which processor will IPL
0B46 2886 Bitstring 1 PFXABFLG CP status flag
1... .... PFXSNPQU X'80' PFXSNPQU This CPU is
quiesced/quiesce pending on
behalf of SNAPDUMP processing
.1.. .... PFXSVCMR X'40' PFXSVCMR CP is obtaining a
frame for SAVBKs
..1. .... PFXABN2 X'20' PFXABN2 This processor
abended while another processor
is already abending.
0B47 2887 Bitstring 1 PFXHSFLG SHARED NAMED SYSTEMS FLAG
1... .... PFXSHRLK X'80' PFXSHRLK PROCESSING SHARED
NAMED SYSTEM PAGE
CPU TIME RESOURCE CONSUMPTION MEASUREMENTS
0B48 2888 Bitstring 8 PFXTMMAX MAXIMUM TIMER VALUE. CONSTANT TO
BE USED FOR INITIALIZING OTHER
FIELDS AND FOR TIMER ARITHMETIC.
0B50 2896 Bitstring 8 PFXTOTWT SYSTEM TOTAL WAIT TIME ON THIS
CPU
0B58 2904 Bitstring 8 PFXPRBTM TOTAL EMULATION STATE TIME FOR
ALL USERS ON THIS CPU
0B60 2912 Bitstring 8 PFXTMSYS SYSTEM TIMER VALUE ON THIS CPU
0B68 2920 Bitstring 8 PFXUTIME TOTAL CPU TIME FOR ALL USERS ON
THIS CPU
0B70 2928 Bitstring 8 PFXACTTS SYSTEM ACCOUNTING TIME, VALUE OF
PFXTMSYS AT LAST 'ACNT' COMMAND
0B78 2936 Bitstring 8 PFXSCITS A copy of PFXTMSYS the last time
it was inspected by the scheduler
running on this CPU. This field
is protected by Scheduler lock
exclusive or a share of Scheduler
lock and SRMATDLK exclusive.
0B80 2944 Bitstring 8 PFXSPINT ELAPSED TIME IN SPIN LOCK ON THIS
CPU STARTING AT ZERO AND COUNTING
UPWARDS
THIS POINTER IS USED TO LOCATE THE TRACE TABLE
PAGES FOR THIS PROCESSOR.
0B88 2952 Signed 4 PFXTTPNT TRACE TABLE PAGES FOR THIS CPU
0B8C 2956 Signed 4 PFXTTPHL HLA of current Trace Table Page.
Must be set to the HLA for the
trace frame PFXCPCRC points to.
MP-CONTROL AND CPU RECOVERY CONTROL FIELDS
0B90 2960 Signed 4 PFXSPINC COUNT OF SPINS ON A SPIN LOCK
0B94 2964 Signed 4 PFXEMSAN EMERGENCY SIGNAL EMSBK ANCHOR
0B98 2968 Address 1 PFXDOWNR TERMINATION REQUEST FIELD
000000FF PFXDOWN 255 PFXDOWN REQUEST FOR
TERMINATION
00000000 PFXDNRZ 000 PFXDNRZ NO REQUEST FOR
TERMINATION
0B99 2969 Address 1 PFXDOWNC TERMINATION COMPLETE FIELD
00000000 PFXDNCZ 000 PFXDNCZ TERMINATION NOT
COMPLETE
000000FF PFXDNEMS 255 PFXDNEMS TERM COMPLETE DUE TO
EMS
000000EE PFXDNRES 238 PFXDNRES TERM COMPLETE DUE TO
RESET
000000DD PFXDNU 221 PFXDNU CPU TERM STATUS
UNKNOWN
000000CC PFXDNSW 204 PFXDNSW Term Complete on
Secondary
0B9A 2970 Address 1 PFXTYPE HOST CPU USAGE TYPE IDENTIFIER
00000000 PFXTYOFL 000 PFXTYOFL CPU IS NOT
OPERATIONAL, SEE PFXSTATE FIELD
FOR DETAILS
00000014 PFXMASTR 020 PFXMASTR THIS IS A
MASTER-TYPE CPU
0000001E PFXTYDED 030 PFXTYDED THIS IS A DEDICATED
CPU
00000028 PFXTYALT 040 PFXTYALT THIS IS AN ALTERNATE
(non-master) TYPE CPU
00000032 PFXPARKD 050 PFXPARKD This is a parked CPU
0B9B 2971 Address 1 PFXDETUP FLAG USED DURING DETECTION FOR
UNRESPONSIVE PROCESSORS
00000000 PFXPRESP 000 PFXPRESP PROCESSOR IS
RESPONSIVE
000000FF PFXTESTP 255 PFXTESTP TEST PROCESSOR
RESPONSIVE
000000CC PFXPRUNR 204 PFXPRUNR PROCESSOR APPEARS
UNRESPONSIVE
00000011 PFXTMOUT 017 PFXTMOUT PROCESSOR IS
UNRESPONSIVE AND IS TIMED OUT
0B9C 2972 Address 1 PFXSTATE CPU OPERATING STATUS
00000000 PFXAVAIL 000 PFXAVAIL CPU IS ONLINE AND
AVAILABLE (SEE PFXTYPE FOR
ALLOWED USAGE)
0000000B PFXRPARK 011 PFXRPARK Attempting to
quiesce this CPU so it can be
parked
00000016 PFXRQUIS 022 PFXRQUIS ATTEMPTING TO
QUIESCE THIS CPU SO IT CAN BE
TAKEN OFFLINE
0000002C PFXVWAIT 044 PFXVWAIT CPU HAS BEEN
QUIESCED AND IS IN DISABLED WAIT
STATE SO IT CAN BE TAKEN OFFLINE
00000037 PFXCSTOP 055 PFXCSTOP CPU IS CHECK-STOPPED
AND HCPMCHCS HAS DEALT WITH IT.
OR IT WAS RESET AND HCPMCWRS HAS
DEALT WITH IT.
00000042 PFXLGOFF 066 PFXLGOFF CPU IS NOW LOGICALLY
OFFLINE
0000006E PFXNOCPU 110 PFXNOCPU CPU IS PHYSICALLY
OFFLINE
000000EE PFXUNKNO 238 PFXUNKNO CPU IS IN AN UNKNOWN
STATE (SIGP COMMUNICATION
FAILURE)
00000082 PFXNEWCP 130 PFXNEWCP CPU IS BEING BROUGHT
ONLINE
0B9D 2973 Bitstring 1 PFXTYPS PFXTYPE SAVEAREA WHILE CPU IS
QUIESCED. Used by SNAPDUMP and
park/unpark processing.
0B9E 2974 Bitstring 1 PFXCPUFL CPU flag used for parking,
unparking, and vary-off
processes. Serialized by by the
Vary Processor Lock (HCPRCCVA).
.... ...1 PFXPRKNG X'01' PFXPRKNG CPU is in parking
process
.... ..1. PFXUNPRK X'02' PFXUNPRK CPU is in
unparking process
.... .1.. PFXPRKOF X'04' PFXPRKOF Varying off a
parked CPU
.... 1... PFXCMDOF X'08' PFXCMDOF Varying off by
command
...1 .... PFXVONFA X'10' PFXVONFA Varying off a CPU
with initialization failure
..1. .... PFXPRKFA X'20' PFXPRKFA Varying off a CPU
with parking failure
.1.. .... PFXUPKFA X'40' PFXUPKFA Varying off a CPU
with unparking failure
1... .... PFXVOFTD X'80' PFXVOFTD Varying off due to
thread deactivation.
0B9F 2975 Bitstring 1 PFXCPUF2 Extension to PFXCPUFL for Vary On
flags.
1... .... PFXVONCM X'80' PFXVONCM Varying on by
command.
.1.. .... PFXVONIN X'40' PFXVONIN Varying on due to
CP initialization.
..1. .... PFXVONTA X'20' PFXVONTA Varying on due to
thread activation.
0BA0 2976 Bitstring 1 PFXMPFLG MP DEFER FLAGS
1... .... PFXCPLOC X'80' PFXCPLOC CP loss of control
checkpoint
.1.. .... PFXLOCTL X'40' PFXLOCTL Loss of control
checkpoint
0BA1 2977 Bitstring 1 PFXMPCNT Flag set if this processor has
been counted in SRMNCPUA.
0BA2 2978 Bitstring 1 PFXPOLAR Current CPU polarization and
entitlement. Valid only when
PFXTYPE is not PFXTYOFL.
Serialized by the Vary Processor
Lock (HCPRCCVA).
00000000 PFXPOLHZ X'00' PFXPOLHZ - Horizontal
00000001 PFXPOLVL X'01' PFXPOLVL - Vertical Low
00000002 PFXPOLVM X'02' PFXPOLVM - Vertical Medium
00000003 PFXPOLVH X'03' PFXPOLVH - Vertical High
0BA3 2979 Address 1 PFXSYNTY Synchronization type
00000000 PFXSYNCL 0 PFXSYNCL None
000000E5 PFXSYNWT C'V' PFXSYNWT HCPSYNWT requested
0BA4 2980 Address 4 PFXDSPBR Addr of HCPDSP internal branch to
optimize work selection
Serialization: block- concurrent
and processor-local See HCPDSP
block comments for details.
0BA8 2984 Signed 4 PFXTSKBK Address of current Task Control
Block
0BAC 2988 Signed 4 PFXTRQOF Address of TRQBK used to delay
storage cleanup at VARY OFF VARY
lock serializes PFXTRQOF.
0BB0 2992 Signed 4 PFXNOLOC A count of the number of
assertions outstanding that the
task running on this CPU cannot
lose control. Serialized by
processor local references only.
0BB4 2996 Address 4 PFXNLADR For debugging: The address of the
last NOLOC or LASTTRANS BEGIN
assertion.
0BB8 3000 Signed 8 PFXNLR15 Save area for R15 (used by
HCPASERT NOLOC)
The following is a copy of the entry in the
SCPINFO CPU description list for this processor.
This field initialized to zeros if the SCLP
interface is not available.
0BC0 3008 Bitstring 16 PFXCPDES (0) CPU description entry
0BC0 3008 Signed 2 * Reserved
0BC2 3010 Bitstring 14 PFXCPFAC (0) CPU Facility bit map
0BC2 3010 Bitstring 1 PFXCPF0 CPU Facility bit map byte 0
0BC3 3011 Bitstring 1 PFXCPF1 CPU FACILITY BIT MAP BYTE 1
0BC4 3012 Bitstring 1 PFXCPF2 CPU Facility bit map byte 2
0BC5 3013 Bitstring 1 PFXCPF3 CPU Facility bit map byte 3
0BC6 3014 Bitstring 1 PFXCPF4 CPU Facility bit map byte 4
0BC7 3015 Bitstring 1 PFXCPF5 CPU Facility bit map byte 5
0BC8 3016 Bitstring 1 PFXCPF6 CPU Facility bit map byte 6
0BC9 3017 Bitstring 1 PFXCPF7 CPU Facility bit map byte 7
0BCA 3018 Bitstring 1 PFXCPF8 CPU Facility bit map byte 8
0BCB 3019 Bitstring 1 PFXCPF9 CPU Facility bit map byte 9
0BCC 3020 Bitstring 1 PFXCPF10 CPU Facility bit map byte 10
0BCD 3021 Bitstring 1 PFXCPF11 CPU Facility bit map byte 11
0BCE 3022 Bitstring 1 PFXCPF12 CPU Facility bit map byte 12
0BCF 3023 Bitstring 1 PFXCPF13 CPU Facility bit map byte 13
0BD0 3024 Signed 2 * (3) Reserved for IBM use
0BD6 3030 Signed 2 PFXCPUAO Logical CPU Address Origin.. this
origin is a bit index
0BD8 3032 Dbl-Word 8 PFXLCPUA Logical CPU Address Note that we
initialize this to 00's so it is
uninitialized in HCPPFX when we
GEN it in. This is because we
don't know on CPU we will be
IPLing.
0BE0 3040 Address 8 * (0) Ensure dw boundary
0BE0 3040 Signed 4 PFXPLSBK PLSBK address for this processor
0BE4 3044 Address 4 PFXEVTBK Trace Services local storage
0BE8 3048 Dbl-Word 8 PFXSAPSW Soft Abend PSW for Asynch dump
0BF0 3056 Signed 4 PFXPGIN Count of fastpath PGINS.
Serialized by Processing list
lock (PLSProLock) due to PLP
reach across case.
0BF4 3060 Signed 4 PFXCLEAR Count of fastpath page fault
resolutions not involving PGINs,
i.e. page clears and copies from
a resident alternate-PTE page.
Serialized by Processing list
lock (PLSProLock) due to PLP
reach across case.
0BF8 3064 Signed 4 PFXCBF Chargeback factor. Updated only
by the single HCPMTCPL task in
the system and when processor
DSVBK assignments are changed.
0BFC 3068 Signed 4 * Reserved for IBM use.
THIS SAVEAREA IS REQUIRED BY HCPPRGIN (PROGRAM
INTERRUPT FLIH) TO AVOID DESTROYING THE CONTENTS
OF PFXIRPSV IN THE CASE OF HCPEXT GETTING A TRACE
PROGRAM INTERRUPT WHILE TRYING TO TRACE AN
EXTERNAL INTERRUPT. THE CONTENTS OF THIS SAVEAREA
WILL BE PLACED IN PFXIRPSV IF IT IS DETERMINED
THAT THE PROGRAM INTERRUPT WAS NOT A TRACE
PROGRAM INTERRUPT.
This area is reserved until the time when HCPPRG
becomes LongReg, at which time it should become
Reserved for IBM.
0C00 3072 Signed 8 PFXPRGSG (5) Scratch area HCPPRG: 5 full regs
0C00 3072 Bitstring 40 PFXPRGSV (0) FLIH save area for HCPPRG
0C00 3072 Signed 4 PFXPRGRC REGISTER 12 ON ENTRY TO HCPPRG
0C04 3076 Signed 4 PFXPRGRD REGISTER 13 ON ENTRY TO HCPPRG
0C08 3080 Signed 4 PFXPRGRE REGISTER 14 ON ENTRY TO HCPPRG
0C0C 3084 Signed 4 PFXPRGRF REGISTER 15 ON ENTRY TO HCPPRG
0C10 3088 Signed 4 PFXPRGR0 REGISTER 0 ON ENTRY TO HCPPRG
0C14 3092 Signed 4 PFXPRGR1 REGISTER 1 ON ENTRY TO HCPPRG
0C18 3096 Signed 4 PFXPRGR2 REGISTER 2 ON ENTRY TO HCPPRG
0C1C 3100 Signed 4 PFXPRGR3 REGISTER 3 ON ENTRY TO HCPPRG
0C20 3104 Signed 4 PFXPRGR4 REGISTER 4 ON ENTRY TO HCPPRG
0C24 3108 Signed 4 PFXPRGR5 REGISTER 5 on entry to HCPPRG
THE FOLLOWING SAVEAREA IS USED BY THE MODULES
WHICH ISSUE THE TRACE INSTRUCTION TO PRESERVE
THE CONTENTS OF THE REGISTERS WHICH ARE USED
TO CONTAIN DATA FOR THE TRACE EVENT BY THE
TRACE INSTRUCTION.
Notes : This area now has a second use, by the TSGET macro
as a temporary save area.
0C28 3112 Bitstring 48 PFXTRCSV (0) Trace instruction save area
0C28 3112 Dbl-Word 8 PFXTRCR0 Save R0 across TRACE instruction
0C30 3120 Dbl-Word 8 PFXTRCR1 Save R1 across TRACE instruction
0C38 3128 Dbl-Word 8 PFXTRCR2 Save R2 across TRACE instruction
0C40 3136 Dbl-Word 8 PFXTRCR3 Save R3 across TRACE instruction
0C48 3144 Dbl-Word 8 PFXTRCR4 Save R4 across TRACE instruction
0C50 3152 Dbl-Word 8 PFXTRCR5 Save R5 across TRACE instruction
0C28 3112 Bitstring 48 PFXTSGSV (0) TSGET save area
0C28 3112 Dbl-Word 8 PFXTSTOD Location for TOD clock
0C30 3120 Dbl-Word 8 PFXTSREG (4) Location for saved work regs
0C50 3152 Signed 4 PFXTSAR (2) Location for saved ARs
THE FOLLOWING AREA IS USED BY MODULE HCPSTP TO
CALCULATE THE SMOOTHED TOTAL RUN TIME FOR EACH
CPU. THE RESULT IS STORED IN PFXSTRN FOR USE
BY THE INDICATE LOAD COMMAND IN CALCULATING THE
CPU UTILIZATION PERCENTAGE.
0C58 3160 Bitstring 40 PFXRNHST (0) RUN HISTORY AREA FOR HCPSTP
0C58 3160 Dbl-Word 8 PFXRNH0 (0)
0C58 3160 Signed 4 PFXRNH00
0C5C 3164 Signed 4 PFXRNH04
0C60 3168 Dbl-Word 8 PFXRNH1 .
0C68 3176 Dbl-Word 8 PFXRNH2 (0) .
0C68 3176 Signed 4 PFXRNH20
0C6C 3180 Signed 4 PFXRNH24
0C70 3184 Dbl-Word 8 PFXRNH3 .
0C78 3192 Dbl-Word 8 PFXRNH4 .
0C80 3200 Dbl-Word 8 PFXFRTC1 Function Related CR12, before
0C88 3208 Dbl-Word 8 PFXFRTC2 Function Related CR12, after
0C90 3216 Dbl-Word 8 * RESERVED FOR IBM USE
0C98 3224 Dbl-Word 8 * RESERVED FOR IBM USE
0CA0 3232 Dbl-Word 8 * RESERVED FOR IBM USE
0CA8 3240 Signed 4 * RESERVED FOR IBM USE
0CAC 3244 Signed 4 PFXSTRN SMOOTHED TOTAL RUN TIME (IN
QUARTER SECONDS)
0CB0 3248 Signed 4 * RESERVED FOR IBM USE
0CB4 3252 Signed 4 PFXINDEX Index into fullword array (i.e.
multiple of 4) based on cpu
address. Note that we initialize
this value to all FF's so when we
gen HCPPFX it can be considered
uninitialized, since we don't
know which CPU we will IPL on.
0CB8 3256 Signed 4 * (9) Unused
0CDC 3292 Address 4 PFXSVRD Trace Services R13 save
The following fields are used by wait-state processing.
0CE0 3296 Signed 4 PFXWTCR6 Copy of host CR6 preserved while
in wait state. This field is only
significant when the PFXWFCR6
flag bit is set.
0CE4 3300 Bitstring 1 PFXWTFLG Flags related to wait-state
processing.
1... .... PFXWFCR6 X'80' PFXWFCR6 When set, host CR6
is preserved in PFXWTCR6.
0CE5 3301 Bitstring 1 PFXSSFLG Read Storage Status
0CE6 3302 Bitstring 1 * (2) Reserved for future IBM use
0CE8 3304 Bitstring 40 PFXWTWRK Wait-state processing work area
The portion of PFXWTWRK used for
parked processors (PFXPKCR0 and
PFXPKFRC) is serialized by the
Vary Processor Lock (HCPRCCVA).
0CE8 3304 Signed 4 PFXIOCOD (3) Results of test pending zone
interruption
0CF4 3316 Signed 4 * Reserved for future IBM use
0CF8 3320 Dbl-Word 8 PFXPKCR0G (0) CR0 before a CPU is parked
0CF8 3320 Signed 4 PFXPKCR0H CR0 high half (reserved)
0CFC 3324 Signed 4 PFXPKCR0 CR0 before a CPU is parked
0D00 3328 Signed 4 PFXPKFRC Return code from a required task
running on a parked CPU
0D04 3332 Signed 4 * (3) Reserved for future IBM use
Miscellaneous PFXPG fields
0D10 3344 Signed 4 PFXFSTPX Count of fast path processing of
partial execution intercepts
0D14 3348 Address 4 PFXCACPG Address of intemediate minidisk
cache buffer (filled in by
HCPMDC).
0D18 3352 Signed 4 PFXABSAD Savearea address at abend. For
HCPABEND MACRO code use only.
0D1C 3356 Signed 4 PFXABRSV Register saveword. For HCPABEND
MACRO code use only.
The following fields are used to store CPU parked
timer and track park time.
PFXPKTOD and PFXPRKWT are fetched and updated
concurrently by CDSG, so no new fields should
be inserted between them.
0D20 3360 Dbl-Word 8 PFXPKTOD A TOD timestamp. Tells when this
CPU was parked. This field will
be zero if the processor is not
parked currently and be updated
with PFXPRKWT by CDSG.
0D28 3368 Dbl-Word 8 PFXPRKWT Accumulated wall clock time for
total parked time. This field
will be updated with PFXPKTOD by
CDSG.
00000B48 PFXPTMER PFXTMMAX CPU timer for park wait
time. This field is only used to
have some reasonable value in the
CPU timer when a CPU is parked,
and not to actually track time
which will be done with TOD
clock.
0D30 3376 Dbl-Word 8 * Reserved for IBM use
The following field is used by LPAR to locate the TOD
clock field in a guest's Accounting Information Area (AIA).
The address of this field must be on a doubleword boundary
and specified between locations 512 and 4088 of the prefix
page. At initialization time, we'll determine if the
64-bit diagnose x'20C' is supported on the machine.
PFXAIAPTG is used for a new-style (64-bit) diag x'20C' and
PFXAIAPT for an old-style (31-bit) diag x'20C'.
0D38 3384 Dbl-Word 8 PFXAIAPTG 64-bit pointer to guest's AIA.TOD
0D38 3384 Address 4 * 64-bit pointer AIA.TOD high half
0D3C 3388 Address 4 PFXAIAPT 31-bit pointer to guest's AIA.TOD
The following word is used by HCPWRP FLIHs as a
temporary save area.
0D40 3392 Signed 4 PFXWRPSV Temporary save area for HCPWRP
0D44 3396 Signed 4 PFXCCTRQ TRQBK committed to the local
clock comparator. Serialized by
use of the TRQBK queue lock.
0D48 3400 Dbl-Word 8 PFXIASIT Work area, which may be used by a
task with no savearea, in which
an i-ASIT may be temporarily
stored. This field is primarily
for GOTO entry points. Any other
routine that uses this field must
be careful that all callers and
all called routines do not
destroy the data nor do so in the
future. PFXIASIT should only be
used for calling entry points
that expressly state that they
can accept input data in this
field.
The following is a copy of the configuration
characteristics field of the Read-SCP-Information
response.
0D50 3408 Bitstring 16 PFXCNFG (0) Configuration Characteristics
0D50 3408 Bitstring 1 PFXCNFG0 Configuration byte 0
0D51 3409 Bitstring 1 PFXCNFG1 Configuration byte 1
0D52 3410 Bitstring 1 PFXCNFG2 Configuration byte 2
0D53 3411 Bitstring 1 PFXCNFG3 Configuration byte 3
0D54 3412 Bitstring 1 PFXCNFG4 Configuration byte 4
0D55 3413 Bitstring 1 PFXCNFG5 Configuration byte 5
0D56 3414 Bitstring 5 * Configuration bytes 6 to 10
0D5B 3419 Bitstring 1 PFXCNFGB Configuration byte 11
0D5C 3420 Bitstring 4 * Configuration bytes 12 to 15
The following field contains bits describing whether
certain architectural facilities are installed. It
describes facilities which have no direct indication in
the PFXCPFAC or PFXCNFG fields. These facilities are
generally tested for via special code.
0D60 3424 Dbl-Word 8 PFXAFAC (0) Architectural facility
indications
0D60 3424 Bitstring 1 PFXAFAC0 Byte 0 of facility flags
1... .... PFXASPO X'80' PFXASPO Storage-Protection
Override
.1.. .... PFXAASP X'40' PFXAASP Asynchronous Paging
..1. .... PFXASGF X'20' PFXASGF Subspace-Group
Facility
...1 .... PFXABSA X'10' PFXABSA Branch and Set
Authority Facility
.... 1... PFXACMM X'08' PFXACMM
.... .1.. PFXADELY X'04' PFXADELY Delay Facility
.... ..1. PFXAIIA X'02' PFXAIIA
.... ...1 PFXBUSY X'01' PFXBUSY
0D61 3425 Bitstring 1 PFXAFAC1 Byte 1 of facility flags
1... .... PFXSEMA X'80' PFXSEMA
.1.. .... PFXIOEA X'40' PFXIOEA
0D62 3426 Bitstring 1 PFXAFAC2 Byte 2 of facility flags
0D63 3427 Bitstring 1 PFXAFAC3 Byte 3 of facility flags
0D64 3428 Bitstring 1 PFXAFAC4 Byte 4 of facility flags
0D65 3429 Bitstring 1 PFXAFAC5 Byte 5 of facility flags
0D66 3430 Bitstring 1 PFXAFAC6 Byte 6 of facility flags
0D67 3431 Bitstring 1 PFXSHELD Shield state for this CPU
.1.. .... PFXSHLON X'40' PFXSHLON Shield activation
selected
Following are some scheduler fields.
0D68 3432 Dbl-Word 8 * Reserved for IBM use
0D70 3440 Dbl-Word 8 PFXATODD A TOD timestamp. When TOD clock
reaches this value, CPU should do
an ATOD-check-in to update
schedul- er's ATOD clock.
(Sometimes equal to SRMATODD, but
sometimes behind.) Updates
serialized by Scheduler lock
exclusive or a share of Scheduler
lock and SRMATDLK exclusive.
0D78 3448 Bitstring 1 * Reserved for IBM use
0DB8 3512 Bitstring 16 PFXMALFM Mask of malfunction alerts
received but not yet handled.
Bits correspond to logical CPU
identifiers of failing CPU's.
(PFXMALFP bit on if non-zero)
0DC8 3528 Signed 4 PFXSLCNT Spin lock counter for C services
0DCC 3532 Signed 4 PFXCTPRG Host logical address of trace
pages' 8 bytes control struct:
'AAAAABBB CCCCCCCC', 'AAAAA000'
is start address, 'BBB' is num of
trace pages, 'CCCCCCCC' is cursor
of trace pages.
0DD0 3536 Signed 4 PFXCVTWK (0) Register savearea for HCPCVTDB
0DD0 3536 Signed 4 PFXCVTW1 GPR1
0DD4 3540 Signed 4 PFXCVTW2 GPR2
0DD8 3544 Signed 4 PFXCVTW3 GPR3
0DDC 3548 Signed 4 PFXCVTW4 GPR4
0DE0 3552 Dbl-Word 8 PFXCVTWX (2) Work area for HCPCVT and HCPIOS
Adcons for dynamic linkage
0DF0 3568 Signed 4 * Reserved for IBM use
0DF4 3572 Signed 4 * Reserved for IBM use
0DF8 3576 Bitstring 16 PFXPSWG Long PSW creation workarea
0E08 3592 Signed 4 * (4) Reserved for IBM use
0E18 3608 Dbl-Word 8 PFXOSIAD (0) OS Info address. C chokes on VD.
0E18 3608 Signed 4 * Do it in pieces for GENH.
0E1C 3612 Address 4 * OS Info address. The value is
also set in absolute page 0 for
stand-alone dump accessibility.
The field is used to generate an
offset to use to set the field
while reverse prefixing. Set at
initialization and never changes.
0E20 3616 Signed 4 * (5) Reserved for IBM use
THE FOLLOWING FIELDS ARE USED BY CP TO KEEP HIGH
PRIORITY USAGE DATA.
0E34 3636 Signed 4 PFXPRGCT Count times purge was requested
at SIE entry (SIEIHCPU=x'FFFF').
0E38 3640 Signed 4 PFXDSPCS COUNT OF FULL SELECT PATHS
THROUGH THE DISPATCHER
0E3C 3644 Signed 4 PFXDSPCT COUNT OF ENTRIES TO DISPATCHER
0E40 3648 Signed 4 PFXDSWCT COUNT OF ENTRIES TO USER WORK
SELECT
0E44 3652 Signed 4 PFXSTKCR COUNT OF TIME-SLICE END REORDERS
0E48 3656 Signed 4 PFXSTKPQ COUNT OF DISPATCH LIST ADDS
0E4C 3660 Signed 4 PFXPTRCT COUNT OF FAST PATH PAGE
TRANSLATIONS
0E50 3664 Signed 4 PFXCTID COUNT OF TIMES THE INTERRUPT
QUEUE LOCK REQUEST IS DEFERRED
0E54 3668 Signed 4 PFXCTIG COUNT OF TIMES THE INTERRUPT
QUEUE LOCK REQUEST IS GRANTED
0E58 3672 Signed 4 PFXCTVD COUNT OF TIMES THE V DEV LOCK
REQUEST IS DEFERRED
0E5C 3676 Signed 4 PFXCTVG COUNT OF TIEMS THE VDEV LOCK
REQUEST IS GRANTED
0E60 3680 Signed 4 PFXRUNCI COUNT OF SIE INTERCEPTIONS
0E64 3684 Signed 4 PFXRUNCP COUNT OF SIE INSTRUCTION
EXECUTIONS
0E68 3688 Signed 4 PFXRUNCR COUNT OF TIMES GUEST'S WORK IS
DISPATCHED
0E6C 3692 Signed 4 PFXRUNPF COUNT OF HOST PAGE FAULTS FOR
GUEST PAGES
0E70 3696 Signed 4 PFXCPUCH Count SIE entries on diff CPU
with SIEIHCPU <> x'FFFF'
0E74 3700 Signed 4 PFXFSTSG Count of fast path simulations of
SIGP External Call instructions.
0E78 3704 Signed 4 PFXFSTXC Count of fast path reflections of
guest External Call interrupts.
0E7C 3708 Signed 4 PFXFST44 Count of fast path simulations of
Diagnose x'44' instructions.
THIS AREA IS RESERVED FOR FE PATCHING. IF NO FE PATCH
IS PROVIDED, THE BR 14 WILL EFFECT A RETURN. THE AREA
AT THE END OF THIS REGION MAY BE USED FOR REGISTER
SAVING. SUBSEQUENT RELEASES OF VM MAY REQUIRE
A REDUCTION IN THE SIZE OF THE PATCHING AREA.
NO PERMANENT USE SHOULD BE ASSIGNED TO THIS AREA.
In a debug build, the PFXPATCH area is not available.
PFXPATCH is always defined with the "BR R14", but
after that, its contents vary.
- in a non-debug build, the remainder of PFXPATCH
is available for patches
- in a debug build, the remainder of PFXPATCH
contains debug code and control pointers
0F00 3840 Signed 2 PFXPINST (64) Room for FE patched instructions
0F80 3968 Signed 4 PFXPSAVE (32) FE Register save area
00001000 PFXPGLEN (*-PFXPG) Size of PFXPG in bytes
The following macro invocation ensures the length of
the PFXPG is exactly 4096 bytes (one 4K page).
This area is page two of the z/Arch prefix area.
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