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Prolog Control Block Contents VECBK DSECT Storage Layout Cross Reference (Contains links to field and bit definitions) |
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VECBK Prolog | Top of page |
NAME : HCPVECBK DESCRIPTION: Vector Register Block DSECT : VECBK FUNCTION : Maps the block that holds guest vector or floating point registers. otes - When a guest logs on, an FPRBK is allocated to save his floating-point registers. If the guest uses vector instructions from the Vector Facility for z/VM then the FPRBK will be released and replaced with a VECBK which has enough room to hold the guest's vector registers. The architecture defines the floating point registers as overlaying the high order 64 bits of vector registers 0-15. It is possible that the guest will switch back to using floating-point registers, so the VECBK has a separate mapping for vector registers and floating-point registers. Although this control block provides a mapping of the floating-point and vector register save area, the actual mapping may differ depending on whether the vector facility is installed and on the length of the vector registers supported by the machine. CP only supports a vector register length of 2DWs now, however, different VR lengths may be supported in the future. For this reason, use VMDVRLEN as the length of the VECFPRnn fields (and thus for the distance between successive VECFPRnn fields). If the vector facility is not installed then VMDVRLEN is 0, the FPRs are 8 bytes each and sequential. They are mapped by the FPRBK. This block is referenced via the address in SIEGVRD. It's size is determined by the number of vector registers (32) and the length of each vector register (2DW). LOCATED BY : VMDFPVRB field in the VMDBK SIEGVRD field in the SIEBK CREATED BY : HCPGIR when the FPRBK is replaced with a VECBK. DELETED BY : HCPUSP at logoff time. SERIALIZED : I-stream elocation Considerations- This control block is relocated as part of a live guest relocation (LGR). The bits and fields that need to be relocated are defined in the $VMDFPRS field of the LGRVMDBK. Additionally, an RDO is passed to the target that contains the vector registers. Whenever changes are made to this control block, consideration must be given to any effects these changes will have on a relocation. If any new fields or bits are defined, they may need to be relocated. If existing bits or fields are changed, corresponding modifications may be required in the LGR version of this control block. Consider also the effects of these changes on a relocation involving a back-level release of CP. |
VECBK Control Block Content | Top of page |
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VECBK Storage Layout | Top of page |
*** VECBK - Vector Register Block * * +-------------------------------------------------------+ * 0 | VECFPR00 | * +-------------------------------------------------------+ * 8 |///////////////////////////////////////////////////////| * +-------------------------------------------------------+ * 10 | VECFPR01 | * +-------------------------------------------------------+ * 18 |///////////////////////////////////////////////////////| * +-------------------------------------------------------+ * 20 | VECFPR02 | * +-------------------------------------------------------+ * 28 |///////////////////////////////////////////////////////| * +-------------------------------------------------------+ * 30 | VECFPR03 | * +-------------------------------------------------------+ * 38 |///////////////////////////////////////////////////////| * +-------------------------------------------------------+ * 40 | VECFPR04 | * +-------------------------------------------------------+ * 48 |///////////////////////////////////////////////////////| * +-------------------------------------------------------+ * 50 | VECFPR05 | * +-------------------------------------------------------+ * 58 |///////////////////////////////////////////////////////| * +-------------------------------------------------------+ * 60 | VECFPR06 | * +-------------------------------------------------------+ * 68 |///////////////////////////////////////////////////////| * +-------------------------------------------------------+ * 70 | VECFPR07 | * +-------------------------------------------------------+ * 78 |///////////////////////////////////////////////////////| * +-------------------------------------------------------+ * 80 | VECFPR08 | * +-------------------------------------------------------+ * 88 |///////////////////////////////////////////////////////| * +-------------------------------------------------------+ * 90 | VECFPR09 | * +-------------------------------------------------------+ * 98 |///////////////////////////////////////////////////////| * +-------------------------------------------------------+ * A0 | VECFPR10 | * +-------------------------------------------------------+ * A8 |///////////////////////////////////////////////////////| * +-------------------------------------------------------+ * B0 | VECFPR11 | * +-------------------------------------------------------+ * B8 |///////////////////////////////////////////////////////| * +-------------------------------------------------------+ * C0 | VECFPR12 | * +-------------------------------------------------------+ * C8 |///////////////////////////////////////////////////////| * +-------------------------------------------------------+ * D0 | VECFPR13 | * +-------------------------------------------------------+ * D8 |///////////////////////////////////////////////////////| * +-------------------------------------------------------+ * E0 | VECFPR14 | * +-------------------------------------------------------+ * E8 |///////////////////////////////////////////////////////| * +-------------------------------------------------------+ * F0 | VECFPR15 | * +-------------------------------------------------------+ * F8 |///////////////////////////////////////////////////////| * +-------------------------------------------------------+ * 100 | VECVR16 | * | | * +-------------------------------------------------------+ * 110 | VECVR17 | * | | * +-------------------------------------------------------+ * 120 | VECVR18 | * | | * +-------------------------------------------------------+ * 130 | VECVR19 | * | | * +-------------------------------------------------------+ * 140 | VECVR20 | * | | * +-------------------------------------------------------+ * 150 | VECVR21 | * | | * +-------------------------------------------------------+ * 160 | VECVR22 | * | | * +-------------------------------------------------------+ * 170 | VECVR23 | * | | * +-------------------------------------------------------+ * 180 | VECVR24 | * | | * +-------------------------------------------------------+ * 190 | VECVR25 | * | | * +-------------------------------------------------------+ * 1A0 | VECVR26 | * | | * +-------------------------------------------------------+ * 1B0 | VECVR27 | * | | * +-------------------------------------------------------+ * 1C0 | VECVR28 | * | | * +-------------------------------------------------------+ * 1D0 | VECVR29 | * | | * +-------------------------------------------------------+ * 1E0 | VECVR30 | * | | * +-------------------------------------------------------+ * 1F0 | VECVR31 | * | | * +-------------------------------------------------------+ * 200 * *** VECBK - Vector Register Block |
VECBK Cross Reference | Top of page |
Symbol Dspl Value -------------- ---- ----- VECFPR00 0000 VECFPR01 0010 VECFPR02 0020 VECFPR03 0030 VECFPR04 0040 VECFPR05 0050 VECFPR06 0060 VECFPR07 0070 VECFPR08 0080 VECFPR09 0090 VECFPR10 00A0 VECFPR11 00B0 VECFPR12 00C0 VECFPR13 00D0 VECFPR14 00E0 VECFPR15 00F0 VECVRS 0000 VECVR00 0000 VECVR01 0010 VECVR02 0020 VECVR03 0030 VECVR04 0040 VECVR05 0050 VECVR06 0060 VECVR07 0070 VECVR08 0080 VECVR09 0090 VECVR10 00A0 VECVR11 00B0 VECVR12 00C0 VECVR13 00D0 VECVR14 00E0 VECVR15 00F0 VECVR16 0100 VECVR17 0110 VECVR18 0120 VECVR19 0130 VECVR20 0140 VECVR21 0150 VECVR22 0160 VECVR23 0170 VECVR24 0180 VECVR25 0190 VECVR26 01A0 VECVR27 01B0 VECVR28 01C0 VECVR29 01D0 VECVR30 01E0 VECVR31 01F0 |
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