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Hex Dec Type/Val Lng Label (dup) Comments
---- ---- --------- ---- -------------- --------
0000 0 Structure TRXBK TRACE EXTENSION BLOCK
Standard savearea for HCPTRX
0000 0 Dbl-Word 8 TRXSAVE (64) STANDARD SAVE AREA **NOTE: THIS
FIELD MUST REMAIN FIRST IN THE
TRXBK. THE HCPTRXNT ENTRY
STATEMENT REFERENCES THE FIELD
WITH 'SAVE=(VMDTREXT)'. Note also
that some of the fields in
TRXSAVE are shared by HCPTRX &
HCPTPX. HCPTRX uses TRXSAVE as
its SAVBK and HCPTPX references
the shared fields through its
addressability to TRXBK
Standard savearea for HCPTPX
0200 512 Dbl-Word 8 TRXTPXSV (64) STANDARD SAVE AREA - used by
HCPTPX
0400 1024 Signed 4 TRXTPXAD Address of above savearea for
linkage
0404 1028 Signed 4 * Reserved for future IBM use
0408 1032 Signed 4 TRXNBASE Base interception bits (without
PER)
040C 1036 Signed 4 TRXECMSK (0) Mask of ECA bits to apply to
VMDECA
040C 1036 Bitstring 1 TRXECAM0 Mask of ECA, byte 0
1... .... SIEECEXT X'80' SIEECEXT External
Interruption Interpretation
Assist
.1.. .... SIEECINT X'40' SIEECINT Intervention
Bypass Assist
..1. .... SIEECWAI X'20' SIEECWAI Guest Wait-State
Assist
...1 .... SIEECSGP X'10' SIEECSGP SIGP
Interpretation Assist
.... 1... SIEECALT X'08' SIEECALT Alert monitoring
bit
.... .1.. SIEECIO2 X'04' SIEECIO2
I/O-Interpretation-level-2
activation bit
.... ...1 SIEECMVP X'01' SIEECMVP MVPG Facility
enablement. When this bit is one,
SIE will inter- pret the MVPG and
IESBE opcodes.
040D 1037 Bitstring 1 TRXECAM1 Mask of ECA, byte 1
.... ..1. SIEECVEC X'02' SIEECVEC Vector Facility
Enablement
040E 1038 Bitstring 1 TRXECAM2 Mask of ECA, byte 2
040F 1039 Bitstring 1 * Reserved for future IBM use
0410 1040 Signed 2 TRXLBASE BASE LCTL INTERCEPTION CONTROLS
0412 1042 Signed 2 TRXTCHBS BASE TCH INTERCEPTION CONTROLS
0414 1044 Bitstring 3 TRXECBMK (0) Mask of ECB bits to apply to
SIEECB
0414 1044 Bitstring 1 TRXECBM0 Mask of ECB, byte 0
0415 1045 Bitstring 1 TRXECBM1 Mask of ECB, byte 1
0416 1046 Bitstring 1 TRXECBM2 Mask of ECB, byte 2
0417 1047 Bitstring 1 * Reserved for future IBM use
Copy of GPRS for base and displacement calculations
When the guest is in ESA/390 mode, the leftmost
half of the registers will be zeros.
0418 1048 Bitstring 128 TRXGGPRS 16 8-byte GPRS
0498 1176 Bitstring 16 TRXGPSW (0) Guest PSW at last call from
RUNU(zArch)
0498 1176 Bitstring 8 TRXPSW (0) GUEST PSW AT LAST CALL FROM
RUNU(390)
0498 1176 Bitstring 4 TRXPSWF1 (0) First fullword of guest PSW
0498 1176 Bitstring 1 TRXPSWB0 Guest PSW byte 0
0499 1177 Bitstring 1 TRXPSWB1 Guest PSW byte 1
049A 1178 Bitstring 1 TRXPSWB2 Guest PSW byte 2
049B 1179 Bitstring 1 TRXPSWB3 Guest PSW byte 3
049C 1180 Signed 4 TRXPSWF2 Second fullword of guest PSW
04A0 1184 Bitstring 8 TRXPSWIA z/Arch PSW instruction address
00000499 TRXPSW1 TRXPSW+1,1 OLD TRCPSW FIELDS FROM
HCPTRD
0000049C TRXPSW4F TRXPSW+4,4 OLD TRCPSW FIELDS FROM
HCPTRD
0000049D TRXPSW57 TRXPSW+5,3 OLD TRCPSW FIELDS FROM
HCPTRD
04A8 1192 Bitstring 16 TRXGBPSW (0) Guest BEFORE EXECUTION PSW
(z/Arch)
04A8 1192 Bitstring 8 TRXBPSW (0) Guest BEFORE EXECUTION PSW (390)
04A8 1192 Bitstring 1 TRXBPSW0 Guest PSW byte 0
04A9 1193 Bitstring 1 TRXBPSW1 Guest PSW byte 1
04AA 1194 Bitstring 1 TRXBPSW2 Guest PSW byte 2
04AB 1195 Bitstring 1 TRXBPSW3 Guest PSW byte 3
04AC 1196 Signed 4 TRXBPSF2 (0) Guest PSW instruction addr
(ESA/390)
04AC 1196 Bitstring 1 TRXBPSW4 Guest PSW byte 4
04AD 1197 Bitstring 1 TRXBPS57 (3) Guest PSW byte 5-7
04B0 1200 Bitstring 1 TRXBPSIA (8) Guest PSW instruction addr
(z/Arch)
04B8 1208 Signed 4 TRXSDSVC SAVED SVC INTERCEPTION CONTROLS
04BC 1212 Signed 2 TRXSDLCT SAVED LCTL INTERCEPTION CONTROLS
04BE 1214 Signed 2 * Reserved for IBM use
04C0 1216 Signed 4 TRXSDNTC Saved instruction interception
controls
04C4 1220 Signed 4 TRXSDECA Saved copy of VMDECA
04C8 1224 Bitstring 1 * Reserved for IBM use
04C9 1225 Bitstring 3 TRXSDECB Saved copy of SIEECB
04CC 1228 Signed 4 * Reserved for IBM use
Adjusted guest control register 9
When the guest is in ESA/390 mode,
the leftmost half of the register will be zeros.
04D0 1232 Dbl-Word 8 TRXGAGCR9 (0) Adjusted guest CR9 (8-bytes)
04D0 1232 Signed 4 * Top half of TRXGAGC9
04D4 1236 Signed 4 TRXAGCR9 ADJUSTED guest CR9 (4-bytes)
04D8 1240 Bitstring 1 TRXVMA SAVE HOST CR6 BYTE 0
04D9 1241 Bitstring 1 TRXTVMA TRACE-ALTERED VMA RUN-MASK
04DA 1242 Signed 2 TRXCRALT LIST OF ALTERED CONTROL REGS
04DC 1244 Signed 4 TRXNXPSW First word of the PSW passed as
input to HCPTRRNX
Guest Control Registers 0 - 15
When the guest is in ESA/390 mode,
the leftmost half of the register will be zeros.
04E0 1248 Bitstring 128 TRXGGCRS Guest Control register values
Guest Control Registers 0 - 15
04E0 1248 Signed 4 TRXGCR0 GUEST CONTROL REGISTER 0
04E4 1252 Signed 4 TRXGCR1 (0) GUEST CONTROL REGISTER 1
04E4 1252 Bitstring 1 TRXGC1B0 Guest CR1 Byte 0
04E5 1253 Bitstring 2 * Guest CR1 Bytes 1-2
04E7 1255 Bitstring 1 TRXGC1B3 Guest CR1 Byte 3
04E8 1256 Signed 4 TRXGCR2 GUEST CONTROL REGISTER 2
04EC 1260 Signed 4 TRXGCR3 GUEST CONTROL REGISTER 3
04F0 1264 Signed 4 TRXGCR4 GUEST CONTROL REGISTER 4
04F4 1268 Signed 4 TRXGCR5 GUEST CONTROL REGISTER 5
04F8 1272 Signed 4 TRXGCR6 GUEST CONTROL REGISTER 6
04FC 1276 Signed 4 TRXGCR7 GUEST CONTROL REGISTER 7
0500 1280 Signed 4 TRXGCR8 GUEST CONTROL REGISTER 8
0504 1284 Signed 4 TRXGCR9 GUEST CONTROL REGISTER 9
0508 1288 Signed 4 TRXGCR10 GUEST CONTROL REGISTER 10
050C 1292 Signed 4 TRXGCR11 GUEST CONTROL REGISTER 11
0510 1296 Signed 4 TRXGCR12 GUEST CONTROL REGISTER 12
0514 1300 Signed 4 TRXGCR13 (0) GUEST CONTROL REGISTER 13
0514 1300 Bitstring 1 TRXGCDB0 Guest CR13 Byte 0
0515 1301 Bitstring 3 * Guest CR13 Bytes 1-3
0518 1304 Signed 4 TRXGCR14 GUEST CONTROL REGISTER 14
051C 1308 Signed 4 TRXGCR15 GUEST CONTROL REGISTER 15
Guest Control Registers 0 - 15
04E0 1248 Dbl-Word 8 TRXGGCR0 GUEST CONTROL REGISTER 0
04E8 1256 Dbl-Word 8 TRXGGCR1 (0) GUEST CONTROL REGISTER 1
04E8 1256 Bitstring 7 * Guest CR1 Bytes 0-6
04EF 1263 Bitstring 1 TRXGGC17 Guest CR1 Byte 7
04F0 1264 Dbl-Word 8 TRXGGCR2 GUEST CONTROL REGISTER 2
04F8 1272 Dbl-Word 8 TRXGGCR3 GUEST CONTROL REGISTER 3
0500 1280 Dbl-Word 8 TRXGGCR4 GUEST CONTROL REGISTER 4
0508 1288 Dbl-Word 8 TRXGGCR5 GUEST CONTROL REGISTER 5
0510 1296 Dbl-Word 8 TRXGGCR6 GUEST CONTROL REGISTER 6
0518 1304 Dbl-Word 8 TRXGGCR7 GUEST CONTROL REGISTER 7
0520 1312 Dbl-Word 8 TRXGGCR8 (0) GUEST CONTROL REGISTER 8
0520 1312 Signed 4 TRXGGCR8HI (0) Left half of guest CR8
0520 1312 Signed 2 *
0522 1314 Signed 2 TRXGGCR8EM Guest CR8 Enhanced-Monitor Masks
0524 1316 Signed 4 TRXGGCR8LO (0) Right half of guest CR8
0524 1316 Signed 2 TRXGGCR8A Guest CR8 Extended Authorization
index
0526 1318 Signed 2 TRXGGCR8M Guest CR8 Monitor Masks
0528 1320 Dbl-Word 8 TRXGGCR9 (0) GUEST CONTROL REGISTER 9
0528 1320 Signed 4 TRXGGCR9HI Left half of guest CR9
052C 1324 Signed 4 TRXGGCR9LO Right half of guest CR9 - PER
info
0530 1328 Dbl-Word 8 TRXGGCR10 GUEST CONTROL REGISTER 10
0538 1336 Dbl-Word 8 TRXGGCR11 GUEST CONTROL REGISTER 11
0540 1344 Dbl-Word 8 TRXGGCR12 GUEST CONTROL REGISTER 12
0548 1352 Dbl-Word 8 TRXGGCR13 (0) GUEST CONTROL REGISTER 13
0548 1352 Bitstring 7 * Guest CR13 Bytes 0-6
054F 1359 Bitstring 1 TRXGGCD7 Guest CR13 Byte 7
0550 1360 Dbl-Word 8 TRXGGCR14 GUEST CONTROL REGISTER 14
0558 1368 Dbl-Word 8 TRXGGCR15 GUEST CONTROL REGISTER 15
Trace Control Registers 0 - 15
When the guest is in ESA/390 mode, the
leftmost half of the registers will be zeros.
0560 1376 Bitstring 128 TRXGTCRS Trace control register values
Trace Control Registers 0 - 15
0560 1376 Signed 4 TRXTCR0 TRACE CONTROL REGISTER 0
0564 1380 Signed 4 TRXTCR1 TRACE CONTROL REGISTER 1
0568 1384 Signed 4 TRXTCR2 TRACE CONTROL REGISTER 2
056C 1388 Signed 4 TRXTCR3 TRACE CONTROL REGISTER 3
0570 1392 Signed 4 TRXTCR4 TRACE CONTROL REGISTER 4
0574 1396 Signed 4 TRXTCR5 TRACE CONTROL REGISTER 5
0578 1400 Signed 4 TRXTCR6 TRACE CONTROL REGISTER 6
057C 1404 Signed 4 TRXTCR7 TRACE CONTROL REGISTER 7
0580 1408 Signed 4 TRXTCR8 TRACE CONTROL REGISTER 8
0584 1412 Signed 4 TRXTCR9 TRACE CONTROL REGISTER 9
0588 1416 Signed 4 TRXTCR10 TRACE CONTROL REGISTER 10
058C 1420 Signed 4 TRXTCR11 TRACE CONTROL REGISTER 11
0590 1424 Signed 4 TRXTCR12 TRACE CONTROL REGISTER 12
0594 1428 Signed 4 TRXTCR13 TRACE CONTROL REGISTER 13
0598 1432 Signed 4 TRXTCR14 TRACE CONTROL REGISTER 14
059C 1436 Signed 4 TRXTCR15 TRACE CONTROL REGISTER 15
Trace Control Registers 0 - 15
0560 1376 Dbl-Word 8 TRXGTCR0 TRACE CONTROL REGISTER 0
0568 1384 Dbl-Word 8 TRXGTCR1 TRACE CONTROL REGISTER 1
0570 1392 Dbl-Word 8 TRXGTCR2 TRACE CONTROL REGISTER 2
0578 1400 Dbl-Word 8 TRXGTCR3 TRACE CONTROL REGISTER 3
0580 1408 Dbl-Word 8 TRXGTCR4 TRACE CONTROL REGISTER 4
0588 1416 Dbl-Word 8 TRXGTCR5 TRACE CONTROL REGISTER 5
0590 1424 Dbl-Word 8 TRXGTCR6 TRACE CONTROL REGISTER 6
0598 1432 Dbl-Word 8 TRXGTCR7 TRACE CONTROL REGISTER 7
05A0 1440 Dbl-Word 8 TRXGTCR8 (0) TRACE CONTROL REGISTER 8
05A0 1440 Signed 4 TRXGTCR8HI (0) Left half of Trace CR8
05A0 1440 Signed 2 *
05A2 1442 Signed 2 TRXGTCR8EM TRACE CR8 Enhanced-Monitor Masks
05A4 1444 Signed 4 TRXGTCR8LO (0) Right half of Trace CR8
05A4 1444 Signed 2 TRXGTCR8A TRACE CR8 Extended Authorization
index
05A6 1446 Signed 2 TRXGTCR8M TRACE CR8 Monitor Masks
05A8 1448 Dbl-Word 8 TRXGTCR9 (0) TRACE CONTROL REGISTER 9
05A8 1448 Signed 4 TRXGTCR9HI Left half of Trace CR9
05AC 1452 Signed 4 TRXGTCR9LO Right half of Trace CR9
05B0 1456 Dbl-Word 8 TRXGTCR10 TRACE CONTROL REGISTER 10
05B8 1464 Dbl-Word 8 TRXGTCR11 TRACE CONTROL REGISTER 11
05C0 1472 Dbl-Word 8 TRXGTCR12 TRACE CONTROL REGISTER 12
05C8 1480 Dbl-Word 8 TRXGTCR13 TRACE CONTROL REGISTER 13
05D0 1488 Dbl-Word 8 TRXGTCR14 TRACE CONTROL REGISTER 14
05D8 1496 Dbl-Word 8 TRXGTCR15 TRACE CONTROL REGISTER 15
Event address for interrupt processor.
NOTES : TRXGEVENT and TRXGIADR must be contiguous.
There is code that does a LMG to load both
of these fields into registers.
05E0 1504 Dbl-Word 8 TRXGEVNT (0) Event address
05E0 1504 Signed 4 * Upper half event address
05E4 1508 Signed 4 TRXEVENT Event address - low
Instruction address (target if EXECUTE instruction)
NOTES : TRXGEVENT and TRXGIADR must be contiguous.
There is code that does a LMG to load both
of these fields into registers.
05E8 1512 Dbl-Word 8 TRXGIADR Instruction address
FIELDS HOLDING P.E.R. INFORMATION ABOUT CURRENT
INSTRUCTION (SUPPLIED BY HCPTRW, HCPTRP, and HCPTPR)
THIS AREA MUST BE CONTIGUOUS TO ALLOW A FAST-CLEAR
VIA XC.
05F0 1520 Dbl-Word 8 TRXTRPNF (0) START OF HCPTRP-SUPPLIED PER INFO
05F0 1520 Signed 2 TRXGPRAM GEN. PURPOSE REGISTER ALTERATION
MAP
05F2 1522 Signed 2 TRXARAM ACCESS REGISTER ALTERATION MAP
05F4 1524 Bitstring 6 TRXEXCUT EXECUTE INSTRUCTION (EX or EXRL)
(ZERO IF NOT PRESENT)
05FA 1530 Character 6 TRXINSTR (0) INSTRUCTION (TARGET INSTR IF
EXECUTE)
05FA 1530 Character 4 TRXINS1F (0) First 4 bytes of target
instruction
05FA 1530 Signed 2 TRXINS1H (0) 1st halfword of target inst
(TRF/TGF)
05FA 1530 Bitstring 1 TRXINSR1 BYTE 1 OF TARGET INSTRUCTION
05FB 1531 Bitstring 1 TRXINSR2 BYTE 2 OF TARGET INSTRUCTION
05FC 1532 Character 4 TRXINS3F (0) Fullword relative offsets
YC9125YL
05FC 1532 Signed 2 TRXINS3H (0) 2nd halfword of target inst (TRF)
05FC 1532 Bitstring 1 TRXINSR3 BYTE 3 OF TARGET INSTRUCTION
05FD 1533 Bitstring 1 TRXINSR4 BYTE 4 OF TARGET INSTRUCTION
05FE 1534 Signed 2 TRXINS5H (0) 3rd halfword of target inst (TRF)
05FE 1534 Signed 2 TRXINS56 (0) LAST TWO BYTES OF TARGET
INSTRUCTION
05FE 1534 Bitstring 1 TRXINSR5 BYTE 5 OF TARGET INSTRUCTION
05FF 1535 Bitstring 1 TRXINSR6 BYTE 6 OF TARGET INSTRUCTION
IF TRXBADRV bit is ONE, TRXBADDR/TRXGBADR addr is valid
0600 1536 Dbl-Word 8 TRXGBADR (0) Successful Branch Address
(64-bit)
0600 1536 Signed 4 * Reserved
0604 1540 Signed 4 TRXBADDR Successful Branch Address
(31-bit)
TRXSADDR contains the address of the instruction's operand
1 (returned from HCPVOPIF).
TRXSLENG is the length of the storage operand at that
address. If the instruction does not cause a storage
alteration at the address in TRXSADDR, then TRXSLENG
will be zero.
TRXSASN, TRXSASCE/TRXSSTD, and TRXSASIT contain addr space
information for this operand.
TRXSFLAG and TRXS1FLG (TRXSINV and TRXSASNF bits) will be
set with information about the operand in TRXSADDR.
NOTES : TRXSADDR comments stated that TRXSADDR is only
valid if bit 0 is 1. No trace code was found to test
this bit so it was deleted when TRXSADDR got a 64-bit
twin.
0608 1544 Dbl-Word 8 TRXSTALT (0)
0608 1544 Dbl-Word 8 TRXGSADR (0) Storage Alteration Address
(64-bit)
0608 1544 Signed 4 * Top half of TRXGSADR
060C 1548 Signed 4 TRXSADDR Storage Alteration Address
(31-bit)
0610 1552 Signed 4 TRXSLENG STORAGE ALTERATION LENGTH
0614 1556 Signed 2 TRXSASN ASN of the address space
containing the first storage
operand. This field is only valid
when the TRXSASNF bit is set.
0616 1558 Bitstring 1 TRXSFLAG ADDRESS SPACE MODE OF STORE
1... .... TRXSHOME X'80' TRXSHOME 'STORE INTO' HOME
.1.. .... TRXSPRI X'40' TRXSPRI 'STORE INTO'
PRIMARY
..1. .... TRXSREAL X'20' TRXSREAL 'STORE INTO' REAL
...1 .... TRXSSEC X'10' TRXSSEC 'STORE INTO'
SECONDARY
.... 1... TRXSAR X'08' TRXSAR 'STORE INTO' AR
0617 1559 Bitstring 1 TRXS1FLG Flags for TRXSADDR
1... .... TRXSUNKN X'80' TRXSUNKN Operand address is
not used
...1 .... TRXSINV X'10' TRXSINV The TRXSASTx field
for this event is inval because
the ALET could not be translated
into an i-ASIT, or the TRXSSTDx
field is invalid because the ALET
could not be translated to a STD.
.... ..1. TRXSASNF X'02' TRXSASNF Storage alt ASN is
saved in TRXSASNx
0618 1560 Dbl-Word 8 TRXSASCE (0) ASCE for storage operand 1
0618 1560 Signed 4 * Top half of TRXSASCE
061C 1564 Signed 4 TRXSSTD STD for storage operand 1
0620 1568 Dbl-Word 8 TRXSASIT Data space i-ASIT of TRXSADDR
TRXSADR2, TRXSADR3, TRXSADR4, and TRXSADR5
contain the addresses of storage operands if the
instruction causes storage alterations at more than
one location.
TRXSLEN2, TRXSLEN3, TRXSLEN4, and TRXSLEN5
contain the lengths of the storage operands in
TRXSADR2-TRXSADR5 if the instruction did indeed cause
storage to be altered at that location.
TRXSASCE/STD2-5, TRXSAST2-5, TRXSASN2-5 and TRXSASC2-5
contain address space information for these operands.
TRXSFLG2-5 and TRXS2FLG-TRXS5FLG (TRXSINVx and TRXASNxF
bits) will be set with information about the
operands in TRXSADR2-5.
0628 1576 Dbl-Word 8 TRXGSAD2 (0) Storage alt addr of 2nd operand
(64bit)
0628 1576 Signed 4 * Top half of TRXGSAD2
062C 1580 Signed 4 TRXSADR2 Storage alt addr of 2nd operand
(31bit)
0630 1584 Signed 4 TRXSLEN2 Storage alt length of second
operand
0634 1588 Signed 2 TRXSASN2 ASN of the address space for
containing TRXSADR2. This field
is only valid when the TRXASN2F
bit is set.
0636 1590 Bitstring 1 TRXSFLG2 Addr space mode of TRXSADR2
0637 1591 Bitstring 1 TRXS2FLG Flags for TRXSADR2
0638 1592 Dbl-Word 8 TRXSASCE2 (0) ASCE for storage operand 2
0638 1592 Signed 4 * Top half of TRXSASCE2
063C 1596 Signed 4 TRXSSTD2 STD for storage operand 2
0640 1600 Dbl-Word 8 TRXSASIT2 Data space i-ASIT of TRXSADR2
0648 1608 Dbl-Word 8 TRXGSAD3 (0) Storage alt addr of 3rd operand
(64bit)
0648 1608 Signed 4 * Top half of TRXGSAD3
064C 1612 Signed 4 TRXSADR3 Storage alt addr of 3rd operand
(31bit)
0650 1616 Signed 4 TRXSLEN3 Storage alt length of third
operand
0654 1620 Signed 2 TRXSASN3 ASN of the address space for
containing TRXSADR3. This field
is only valid when the TRXASN3F
bit is set.
0656 1622 Bitstring 1 TRXSFLG3 Addr space mode of TRXSADR3
0657 1623 Bitstring 1 TRXS3FLG Flags for TRXSADR3
0658 1624 Dbl-Word 8 TRXSASCE3 (0) ASCE for storage operand 3
0658 1624 Signed 4 * Top half of TRXSACE3
065C 1628 Signed 4 TRXSSTD3 STD for storage operand 3
0660 1632 Dbl-Word 8 TRXSASIT3 Data space i-ASIT of TRXSADR3
0668 1640 Dbl-Word 8 TRXGSAD4 (0) Storage alt addr of 4th operand
(64bit)
0668 1640 Signed 4 * Top half of TRXGSAD4
066C 1644 Signed 4 TRXSADR4 Storage alt addr of 4th operand
(31bit)
0670 1648 Signed 4 TRXSLEN4 Storage alt length of fourth
operand
0674 1652 Signed 2 TRXSASN4 ASN of the address space for
containing TRXSADR4. This field
is only valid when the TRXASN4F
bit is set.
0676 1654 Bitstring 1 TRXSFLG4 Addr space mode of TRXSADR4
0677 1655 Bitstring 1 TRXS4FLG Flags for TRXSADR4
0678 1656 Dbl-Word 8 TRXSASCE4 (0) ASCE for storage operand 4
0678 1656 Signed 4 * Top half of TRXSASCE4
067C 1660 Signed 4 TRXSSTD4 STD for storage operand 4
0680 1664 Dbl-Word 8 TRXSASIT4 Data space i-ASIT of TRXSADR4
0688 1672 Dbl-Word 8 TRXGSAD5 (0) Storage alt addr of 5th operand
(64bit)
0688 1672 Signed 4 * Top half of TRXGSAD5
068C 1676 Signed 4 TRXSADR5 Storage alt addr of 5th operand
(31bit)
0690 1680 Signed 4 TRXSLEN5 Storage alt length of fifth
operand
0694 1684 Signed 2 TRXSASN5 ASN of the address space for
containing TRXSADR5. This field
is only valid when the TRXASN5F
bit is set.
0696 1686 Bitstring 1 TRXSFLG5 Addr space mode of TRXSADR5
0697 1687 Bitstring 1 TRXS5FLG Flags for TRXSADR5
0698 1688 Dbl-Word 8 TRXSASCE5 (0) ASCE for storage operand 5
0698 1688 Signed 4 * Top half of TRXSASCE5
069C 1692 Signed 4 TRXSSTD5 STD for storage operand 5
06A0 1696 Dbl-Word 8 TRXSASIT5 Data space i-ASIT of TRXSADR5
000000A0 TRXSALTL *-TRXSTALT Length of storage Alt
data
000000B8 TRXTRPNL *-TRXTRPNF Lenght of
HCPTRW/HCPTRP supplied PER
information in bytes
06A8 1704 Dbl-Word 8 TRXCASCE (0) Data space ASCE of current
instruction
06A8 1704 Signed 4 * Reserved for current ASCE
06AC 1708 Signed 4 TRXCSTD DATA SPACE STD OF CURRENT
INSTRUCTION
06B0 1712 Dbl-Word 8 TRXDASCE (0) Data space ASCE of branch
06B0 1712 Signed 4 * Reserved for destination ASCE
06B4 1716 Signed 4 TRXDSTD DATA SPACE STD OF BRANCH
06B8 1720 Dbl-Word 8 TRXRCASCE (0) Recomputation ASCE
06B8 1720 Signed 4 * Reserved for recomputation ASCE
06BC 1724 Signed 4 TRXRCSTO RECOMPUTATION STO
06C0 1728 Signed 2 TRXRCASN Recomputation ASN. This field is
only valid when the TRXRASNF bit
is set.
06C2 1730 Signed 2 TRXDASN Destination ASN of current branch
event. This field is only valid
when the TRXDASNF bit is set.
06C4 1732 Bitstring 1 TRXAFLAG INDICATE ADDRESS SPACE MODE
1... .... TRXDHOME X'80' TRXDHOME 'BRANCH TO' HOME
.1.. .... TRXDPRI X'40' TRXDPRI 'BRANCH TO' PRIMARY
..1. .... TRXDREAL X'20' TRXDREAL 'BRANCH TO' REAL
...1 .... TRXDSEC X'10' TRXDSEC 'BRANCH TO'
SECONDARY
.... 1... TRXDAR X'08' TRXDAR 'BRANCH TO' AR
.... .1.. TRXHOME X'04' TRXHOME INSTRUCTION
EXECUTED IN HOME
.... ..1. TRXPRI X'02' TRXPRI INSTRUCTION EXECUTED
IN PRIMARY
.... ...1 TRXREAL X'01' TRXREAL INSTRUCTION
EXECUTED IN REAL
06C5 1733 Bitstring 1 * (3) Reserved for IBM use
06C8 1736 Signed 4 * Reserved for IBM use
ANCHOR LIST OF RANGES FOR GAP LIST CONSTRUCTION
06CC 1740 Address 4 TRXRNGAN ANCHOR FOR OUR LIST OF RANGES.
REPRESENTATION OF USER P.E.R. AS PROPER RANGES
06D0 1744 Address 4 TRXARNG1 POINTER FOR THE FIRST SECTION OF
RANGE
06D4 1748 Signed 4 * Reserved
06D8 1752 Dbl-Word 8 TRXGRNG1 (2) First range of guest PER range
06E8 1768 Address 4 TRXARNG2 POINTER FOR THE SECOND SECTION OF
RANGE
06EC 1772 Signed 4 * Reserved
06F0 1776 Dbl-Word 8 TRXGRNG2 (2) second range of guest PER range
COUNTERS FOR UTILIZATION LIMITS/STATISTICS
0700 1792 Signed 2 TRXNOTRS NUMBER OF TRACE SETS DEFINED
0702 1794 Signed 2 TRXNOTRP NUMBER OF TRAPS DEFINED
POINTERS TO CURRENT CONTROL BLOCKS
0704 1796 Address 4 TRXTRSET POINTER TO CURRENT TRACE SET
DESCRIPTOR
0708 1800 Signed 4 TRXRETRN CURRENT CALL/RETURN SET ADDRESS
070C 1804 Signed 4 * Reserved
0710 1808 Signed 4 TRXGAP POINTER TO CURRENT GAP MEMBER
0714 1812 Signed 4 TRXGAPDW NUMBER OF DOUBLEWORDS IN GAP
LIST.
0718 1816 Address 4 TRXGAPAD Address of storage obtained for
the gap list. This may be
different from the address in
TRXGAPS because TRXGAPS must be
on a quadword boundary.
071C 1820 Address 4 TRXGAPS POINTER TO CURRENT GAP LIST
0720 1824 Address 4 TRXGAPL LOWER BOUND GAP LIST ADDRESS
0724 1828 Address 4 TRXGAPU UPPER BOUND GAP LIST ADDRESS
0728 1832 Signed 4 TRXCOUNT CURRENT VALUE OF TRACE COUNT
072C 1836 Address 4 TRXTBTBK POINTER TO TRACEBACK TABLE
CP COMMAND STATUS INFORMATION
0730 1840 Address 4 TRXCP1ST POINTER TO FIRST CP COMMAND
0734 1844 Address 4 TRXCPLST POINTER TO LAST CP COMMAND
DISPLAY PARAMETERS FOR INTERRUPTIONS
0738 1848 Signed 4 TRXDYEXT (4) EXT ADDR, CODES
0748 1864 Signed 4 TRXDYPRG (4) PROG ADDR, CODES
0758 1880 Signed 4 TRXDYIO (4) I/O ADDR, CODES
0768 1896 Signed 4 TRXDYMCH (10) MACH. CHECK ADDR.,FLAGS,CODES,FSA
INSTRUCTION DISPLAY INFORMATION
0790 1936 Signed 2 TRXDIOS I/O TRACING INFORMATION
0792 1938 Signed 2 TRXGPRBT GPR BIT MASK FOR TERMINAL
0794 1940 Signed 2 TRXGPRBP GPR BIT MASK FOR PRINTER
0796 1942 Signed 2 TRXARBT AR BIT MASK FOR TERMINAL
0798 1944 Signed 2 TRXARBP AR BIT MASK FOR PRINTER
079A 1946 Bitstring 1 TRXDINST INSTRUCTION INFO
079B 1947 Bitstring 1 TRXFLAG TRACE FLAG BYTE
1... .... TRXDOPER X'80' TRXDOPER PERFORM PER ON
CURRENT EVENT
.1.. .... TRXEVSET X'40' TRXEVSET EVENT ADDRESS IS
SET
..1. .... TRXHVPER X'20' TRXHVPER PER INFORMATION
PRESENT
...1 .... TRXTPSW X'10' TRXTPSW TRXPSW IS SET
.... 1... TRXDATA X'08' TRXDATA STORAGE DATA TRAPS
PENDING
.... .1.. TRXCFMOD X'04' TRXCFMOD PLACE USER INTO
CONSOLE FUNC MODE
.... ..1. TRXCNCLT X'02' TRXCNCLT TERMINAL OUTPUT
CANCELLED
.... ...1 TRXCNCLP X'01' TRXCNCLP PRINTER OUTPUT
CANCELLED
CONTROL INFORMATION
079C 1948 Bitstring 1 TRXCATEG TRACING CONTROL CATEGORY SUMMARY
079D 1949 Bitstring 1 TRXPERCT PER TRACING SCREENING SUMMARY
079E 1950 Bitstring 1 TRXSTATS TRACE STATUS CONTROL FLAG
1... .... TRXRLINK X'80' TRXRLINK RE-LINK TRAP
RANGES AND RE-ALLOCATE GAP LIST
.1.. .... TRXRSORT X'40' TRXRSORT RE-SORT RANGES
BEFORE RE-COMPUTING GAPS.
..1. .... TRXRCOMP X'20' TRXRCOMP RE-COMPUTE THE GAP
LIST.
...1 .... TRXRSRCH X'10' TRXRSRCH RESEARCH GAP LIST
FOR IFETCH/STORE
.... 1... TRXSUSP X'08' TRXSUSP CURRENT SET IS IN
SUSPENSION
.... .1.. TRXPERTR X'04' TRXPERTR HYPERVISOR P.E.R.
TRACING IS ACTIVE
.... ..1. TRXSVCTR X'02' TRXSVCTR SOME FORM OF SVC
TRACING IS IN EFFECT
.... ...1 TRXINULL X'01' TRXINULL INSTRUCTION
EXECUTION NULLIFIED
079F 1951 Bitstring 1 TRXSTAT2 TRACE STATUS CONTROL FLAG
1... .... TRXMCALT X'80' TRXMCALT GUEST ALTERED FOR
MONITOR-CALL TRACING
.1.. .... TRXPPNEM X'40' TRXPPNEM MNEMONIC POST-SCAN
REQUIRED
..1. .... TRXICNCL X'20' TRXICNCL INSTRUCTION
EXECUTION CANCELLED
...1 .... TRXIPOST X'10' TRXIPOST ANALYZE
INSTRUCTION POST SIM.
.... 1... TRXIPROG X'08' TRXIPROG PROGRAM EXCEP
DURING INSTR SIM.
.... .1.. TRXIBSET X'04' TRXIBSET BRANCH ADDRESS SET
FOR INSTR
.... ..1. TRXIUNKN X'02' TRXIUNKN UNKNOWN STORAGE
ALTERATION
.... ...1 TRXIREAL X'01' TRXIREAL ALTERATION TO REAL
STORAGE ADDR
..11 1111 TRXISTAT X'3F' TRXISTAT BITS IN TRXSTAT2
FOR INSTR STATUS
07A0 1952 Bitstring 1 TRXSTAT3 MISCELLANEOUS TRACE STATUS
1... .... TRXCTACT X'80' TRXCTACT TRACE COUNT IS
ACTIVE
.1.. .... TRXSTURA X'40' TRXSTURA A STURA EVENT HAS
OCCURRED
..1. .... TRXIFT X'20' TRXIFT Instruction Fetch
Filtering bit Indicates that at
least one PER type trap is
restricted to instructions which
are fetched from a specific
address space. When this bit is
set, TRACE needs to keep track of
which address space instructions
are fetched from, and get
notified whenever that changes.
.... 1... TRXIADSP X'08' TRXIADSP Instruction Fetch
Address Space Filtering Indicates
that at least one trace trap is
resticted to instructions that
are fetched from a specific 370
or ESA mode address space. When
this bit is set, TRACE needs to
keep current address space
information in TRXRCSTO,TRXRCASCE
and TRXRCASN.
.... .1.. TRXRASNF X'04' TRXRASNF Recomputation ASN
is saved in TRXRCASN
.... ...1 TRXDASNF X'01' TRXDASNF Destination ASN of
branch event is saved in TRXDASN
07A1 1953 Bitstring 1 TRXSTAT4 Miscellaneous TRACE status
1... .... TRXHITCT X'80' TRXHITCT A trap has hit
which should cause the trace
count to be incremented if TRACE
COUNT is active.
.1.. .... TRXST4K X'40' TRXST4K A stg alteration
occurred within 4K bytes of the
storage operand address
..1. .... TRXSTFLE X'20' TRXSTFLE A TRACE STFLE trap
exists
.... 1... TRXBPSWF X'08' TRXBPSWF TRXBPSW has been
created
.... .1.. TRXPLOST X'04' TRXPLOST HCPTPIPL obtained
PLO plist STorage which
HCPTPR/HCPTGL needs to free
.... ..1. TRXQMARK X'02' TRXQMARK HCPTGDFA routine
should format question marks
instead of R1 address
.... ...1 TRXBADRV X'01' TRXBADRV TRXBADDR/TRXGBADR
branch addr is valid
TRXS1FLG, TRXS2FLG, TRXS3FLG, TRXS4FLG, and TRXS5FLG
contain flag bytes for TRXSADDR, TRXSADR2-TRXSADR5.
These flag bytes must remain contiguous because
they are cleared using one instruction in HCPTRW.
07A2 1954 Bitstring 1 * (3) Reserved for IBM use
07A8 1960 Dbl-Word 8 TRXTMPSW PSW ADDR AT LAST DISPLAY TO
TERMINAL
07B0 1968 Dbl-Word 8 TRXPRPSW PSW ADDR AT LAST DISPLAY TO
PRINTER
07B8 1976 Signed 4 TRXCCWBF SYSTEM VIRTUAL ADDR OF CCW TRACE
BUFFER
07BC 1980 Character 4 TRXMPPFX NN PREFIX FOR VIRTUAL MP OUTPUT
07C0 1984 Character 96 TRXBUFF BUFFER FOR TERMINAL/PRINTER
OUTPUT
Work Area used by HCPTRX, HCPTRY, HCPTRP, HCPTPI
0820 2080 Dbl-Word 8 TRXWORK (0) Start of Work Space
0820 2080 Dbl-Word 8 TRXWASIT i-ASIT of storage operand
0828 2088 Dbl-Word 8 TRXWASCE (0) ASCE of storage operand
0828 2088 Signed 4 * Top half of ASCE
082C 2092 Signed 4 TRXWSTD STD of storage operand
0830 2096 Signed 2 TRXWASN ASN of storage operand
0832 2098 Bitstring 1 TRXWFLG1 Flag byte
...1 .... TRXWINV X'10' TRXWINV The TRXWASIT field
for this event is inval because
the ALET could not be translated
into an i-ASIT, or the TRWSTD
field is invalid because the ALET
could not be translated to a STD.
.... ..1. TRXWASNF X'02' TRXWASNF Storage alt ASN is
saved in TRXWASN
0833 2099 Bitstring 1 TRXWSFLG bits for TRXWSFLG defined in
TRXSFLAG
00000014 TRXWORKL *-TRXWORK Length of Work Area
DISPLAY PARAMETERS FOR IUCV/APPC INSTRUCTIONS
0834 2100 Character 8 TRXIUCVF IUCV/APPC Function name
Facility List Designation used by STLFE instruction
083C 2108 Signed 4 TRXFLD FLD
Transactional Execution section
0840 2112 Bitstring 1 TRXTXFLG Trace Transactional Execution
Flags
1... .... TRXTXTXA X'80' TRXTXTXA Guest transaction
aborted. This flag is set from
HCPTRXNT and HCPTPXPM when we
save information from the ITDB.
It is reset at that back end of
HCPTRGRUN just before running the
guest. When this bit is one, the
following fields and flags are
valid: TRXTXFM1 TRXTXADR
.1.. .... TRXTXFM1 X'40' TRXTXFM1 Format-1 TDB is
available. This flag is valid
only when TRXTXTXA is set. When
this flag is one, the following
fields are valid: TRXTAFLG
TRXTATIA
0841 2113 Bitstring 1 TRXTAFLG TDBFLAGS at time of abort
0842 2114 Bitstring 2 * reserved
0848 2120 Signed 8 TRXTXADR Transaction abort addr or
Transaction begin address
calcualted from SIEPSWIA
0850 2128 Signed 8 TRXTATIA Transaction abort instruction
address TDBATIA ****** End of
Transactional Execution section
0858 2136 Dbl-Word 8 TRXEND (0) END OF TRACE CONTROL BLOCK
0000010B TRXSIZE (*-TRXBK+7)/8 NUMBER OF
DOUBLEWORDS IN BLOCK.
*****
***** Redefinitions of Previously Defined Fields
*****
Information for machine checks is gathered in
HCPTPXMC and stored in the following fields.
0768 1896 Dbl-Word 8 TRXMCGA Machine check old PSW address
0770 1904 Bitstring 1 TRXMCFLG (2) FLAGS FOR TERM/PRINT OPTION
0772 1906 Bitstring 1 * (2) RESERVED
0774 1908 Signed 4 * Resreved
0778 1912 Signed 4 TRXMCINT (2) MACHINE CHECK INTERRUPT BITS
0780 1920 Dbl-Word 8 TRXMCHFA Machine check failing storage
i-ASIT
0788 1928 Dbl-Word 8 TRXGMFSA (0) FAILING STORAGE ADDRESS
0788 1928 Signed 4 * Reserved - z/Arch FSA
078C 1932 Signed 4 TRXMCFSA FAILING STORAGE ADDRESS - 370
Information for external interrupts is gathered in
HCPTPXEX and stored in the following fields.
0738 1848 Bitstring 8 TRXEXTGA External old PSW address
0740 1856 Signed 4 TRXEXTFL TERM/PRINT flags, event code
0744 1860 Signed 4 * Reserved
Information for program interrupts is gathered in
HCPTPXPM and stored in the following fields.
0748 1864 Bitstring 8 TRXPRGGA (0) Program old PSW address - z/Arch
guest
0748 1864 Signed 4 *
074C 1868 Signed 4 TRXPRGAD Program old PSW address - ESA/390
guest
0750 1872 Signed 4 TRXPRGFL TERM/PRINT flags, event code
0754 1876 Signed 4 * Reserved
Information for IO interrupts is gathered in
HCPTPXIO and stored in the following fields.
0758 1880 Bitstring 8 TRXIOGA I/O old PSW address
0760 1888 Signed 4 TRXIOFL TERM/PRINT flags, event code
0764 1892 Bitstring 1 TRXIOFLG Indicate an AIF interrupt
1... .... TRXIOAIF X'80' TRXIOAIF - This is an AIF
interrupt
0765 1893 Bitstring 1 * Reserved
0766 1894 Signed 2 TRXIODNN Active IODATA byte count
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