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Hex Dec Type/Val Lng Label (dup) Comments
---- ---- --------- ---- -------------- --------
0000 0 Structure PAGG Page Table Entry for z/Architecture
0000 0 Dbl-Word 8 PAGGENTR PTEs are 8 bytes in z/Arch
0000 0 Signed 4 PAG64W0 (0) PTE Word 0
0000 0 Signed 4 PAGGPFRL Bits 0-31 of 64 bit PFRA
0004 4 Signed 4 PAGGPFRR Bits 32-51 of 64 bit PFRA, plus
status bits
00000008 PAGGLENG *-PAGGENTR Length of 1 PTE
00000003 PAGGSZSHF 3 Shift value to multiply by size
of a PTE
0008 8 Signed 4 PAGGNEXT (0) Next Page Table Entry
0000 0 Signed 4 * Architected as bits 0-31 of the
4K aligned page frame real
address (if page is resident)
0004 4 Signed 2 * Architected as bits 32-47 of the
4K aligned page frame real
address (if page is resident)
0006 6 Bitstring 1 PAGGSTAT Architected as bits 48-51 of the
4K aligned page frame real
address (if page is resident),
followed by four flag bits:
1111 .... PAGGSPFR X'F0' PAGGSPFR Bits 48-51 of PFRA
(if resident)
.... 1..1 PAGGSMBZ X'09' PAGGSMBZ Must be zero in
any valid PTE
.... .1.. PAGGINVA X'04' PAGGINVA Page-Table Entry
is invalid
.... ..1. PAGGPROT X'02' PAGGPROT PTE is page
protected-read only
0007 7 Bitstring 1 PAGGSTA2 Has 7 reserved bits and lock bit
1111 111. PAGGS2PG X'FE' PAGGS2PG Reserved bits
.... ...1 PAGGS2LK X'01' PAGGS2LK Lock bit (used by
LKPG) 64-bit mask
X'FFFFFFFFFFFFF800' to compute a
PTO from a PTE address.
PAGGSTA2 PAGGPTMH X'FFFFFFFF' PAGGPTMH Isolate high
half of PTOM
PAGGSTA2 PAGGPTML X'FFFFF800' PAGGPTML Isolate low
half of PTOM 64-bit mask
X'FFFFFFFFFFFFF000' - See
PFXGPFRA.
PAGGSTA2 PAGGPFAH X'FFFFFFFF' PAGGPFAH Isolate high
half of PFRA
PAGGSTA2 PAGGPFAL X'FFFFF000' PAGGPFAL Isolate low
half of PFRA 64-bit mask
X'0000000000000400' 32-bit high
X'00000000' High half of mask
PAGGSTA2 PAGGINVR X'00000400' PAGGINVR Isolate I
bit 64-bit mask
X'0000000000000200' 32-bit high
X'00000000' High half of mask
PAGGSTA2 PAGGPROR X'00000200' PAGGPROR Isolate P
bit 64-bit mask
X'0000000000000900' 32-bit high
X'00000000' High half of mask
PAGGSTA2 PAGGRSVR X'00000900' PAGGRSVR Reserved
bits, must be 0 in any valid
z/Arch PTE 64-bit mask
X'0000000000000001' 32-bit high
X'00000000' High half of mask
.... ...1 PAGGXSLR X'00000001' PAGGXSLR Isolate L
bit (Lock bit)
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