PAGG

Prolog  

Control Block Contents  
   PAGG DSECT

Storage Layout  

Cross Reference (Contains links to field and bit definitions)  

PAGG Prolog

 Name       : HCPPAGG
 Description: Page Table Entry for z/Architecture
 DSECT      : PAGG
 Function   : A Page Table Entry is a hardware architected
              area that describes one 4K page of virtual
              storage.

PAGG Control Block Content

PAGG DSECT

Hex   Dec Type/Val   Lng Label (dup)    Comments
---- ---- --------- ---- -------------- --------
0000    0 Structure      PAGG           Page Table Entry for z/Architecture
0000    0 Dbl-Word     8 PAGGENTR       PTEs are 8 bytes in z/Arch
0000    0 Signed       4 PAG64W0 (0)    PTE Word 0
0000    0 Signed       4 PAGGPFRL       Bits 0-31 of 64 bit PFRA
0004    4 Signed       4 PAGGPFRR       Bits 32-51 of 64 bit PFRA, plus
                                        status bits
          00000008       PAGGLENG       *-PAGGENTR Length of 1 PTE
          00000003       PAGGSZSHF      3 Shift value to multiply by size
                                        of a PTE
0008    8 Signed       4 PAGGNEXT (0)   Next Page Table Entry
0000    0 Signed       4 *              Architected as bits 0-31 of the
                                        4K aligned page frame real
                                        address (if PTE is valid)
0004    4 Signed       2 *              Architected as bits 32-47 of the
                                        4K aligned page frame real
                                        address (if PTE is valid)
0006    6 Bitstring    1 PAGGSTAT       Architected as bits 48-51 of the
                                        4K aligned page frame real
                                        address (if valid in storage),
                                        followed by four flag bits:
          1111 ....      PAGGSPFR       X'F0' PAGGSPFR Bits 48-51 of PFRA
                                        (if valid)
          .... 1..1      PAGGSMBZ       X'09' PAGGSMBZ Must be zero in
                                        any valid PTE
          .... .1..      PAGGINVA       X'04' PAGGINVA Page-Table Entry
                                        is invalid
          .... ..1.      PAGGPROT       X'02' PAGGPROT PTE is page
                                        protected-read only
0007    7 Bitstring    1 PAGGSTA2       Has 7 reserved bits and lock bit
          1111 111.      PAGGS2PG       X'FE' PAGGS2PG Reserved bits
          .... ...1      PAGGS2LK       X'01' PAGGS2LK Lock bit (used by
                                        LKPG) 64-bit mask
                                        X'FFFFFFFFFFFFF800' to compute a
                                        PTO from a PTE address.
          PAGGSTA2       PAGGPTMH       X'FFFFFFFF' PAGGPTMH Isolate high
                                        half of PTOM
          PAGGSTA2       PAGGPTML       X'FFFFF800' PAGGPTML Isolate low
                                        half of PTOM 64-bit mask
                                        X'FFFFFFFFFFFFF000' - See
                                        PFXGPFRA.
          PAGGSTA2       PAGGPFAH       X'FFFFFFFF' PAGGPFAH Isolate high
                                        half of PFRA
          PAGGSTA2       PAGGPFAL       X'FFFFF000' PAGGPFAL Isolate low
                                        half of PFRA 64-bit mask
                                        X'0000000000000400' 32-bit high
                                        X'00000000' High half of mask
          PAGGSTA2       PAGGINVR       X'00000400' PAGGINVR Isolate I
                                        bit 64-bit mask
                                        X'0000000000000200' 32-bit high
                                        X'00000000' High half of mask
          PAGGSTA2       PAGGPROR       X'00000200' PAGGPROR Isolate P
                                        bit 64-bit mask
                                        X'0000000000000900' 32-bit high
                                        X'00000000' High half of mask
          PAGGSTA2       PAGGRSVR       X'00000900' PAGGRSVR Reserved
                                        bits, must be 0 in any valid
                                        z/Arch PTE 64-bit mask
                                        X'0000000000000001' 32-bit high
                                        X'00000000' High half of mask
          .... ...1      PAGGXSLR       X'00000001' PAGGXSLR Isolate L
                                        bit (Lock bit)

PAGG Storage Layout

          
*** PAGG - Page Table Entry for z/Architecture
*
*     +-------------------------------------------------------+
*   0 |                       PAGGENTR                        |
*     +-------------------------------------------------------+
*   8
*
*** PAGG - Page Table Entry for z/Architecture
          
*** Overlay for PAGGENTR in PAGG
*
*     +---------------------------+---------------------------+
*   0 |         PAGGPFRL          |         PAGGPFRR          |
*     +---------------------------+---------------------------+
*
*** Overlay for PAGGENTR in PAGG
          
*** Overlay for PAGGENTR in PAGG
*
*     +---------------------------+-------------+------+------+
*   0 |///////////////////////////|/////////////|:GSTAT|:GSTA2|
*     +---------------------------+-------------+------+------+
*   8
*
*** Overlay for PAGGENTR in PAGG

PAGG Cross Reference

Symbol         Dspl Value
-------------- ---- -----
PAGGENTR       0000
PAGGINVA       0006 04
PAGGINVR       0007 PAGGSTA2
PAGGLENG       0004 00000008
PAGGNEXT       0008
PAGGPFAH       0007 PAGGSTA2
PAGGPFAL       0007 PAGGSTA2
PAGGPFRL       0000
PAGGPFRR       0004
PAGGPROR       0007 PAGGSTA2
PAGGPROT       0006 02
PAGGPTMH       0007 PAGGSTA2
PAGGPTML       0007 PAGGSTA2
PAGGRSVR       0007 PAGGSTA2
PAGGSMBZ       0006 09
PAGGSPFR       0006 F0
PAGGSTAT       0006
PAGGSTA2       0007
PAGGSZSHF      0004 00000003
PAGGS2LK       0007 01
PAGGS2PG       0007 FE
PAGGXSLR       0007 01
PAG64W0        0000