Programming Interface Information:
This information is NOT intended to be used as Programming Interfaces of z/VM. |
PAGTE
Control Block Contents
PAGTE DSECT
Cross Reference (Contains links to field and bit definitions)
PAGTE Prolog
Name : HCPPAGTE Description: Page Table Entry DSECT : PAGTE Function : A Page Table Entry is a hardware architected area that describes one 4K page of virtual storage. In ESA/390 mode, Page Table Entries are one word (4 bytes) in length. In ESAME mode, page table entries are one doubleword (8 bytes) in length. Located by : ESA/390 mode: PGMPAGTB in a PGMBK + (page offset * 4) FRMPTE field of HCPFRMTE (31 bit address) ESAME mode: PGMPAGTB in a PGMBK + (page offset * 8) FRMPTE field of HCPFRMTE (31 bit address) A page table resides in a Page Management Block (PGMBK) associated with a megabyte of virtual storage, and is located by PGMPAGTB and pointed to by the Page Table Origin (PTO) portion of a valid Segment Table Entry (STE). There are (up to) 256 contiguous page table entries in a page table. (ESA/390 page tables may have less than than 256 entries, depending on the Page Table Length field SEGPTL in the STE associated with the page table. ESAME page tables must always be a full 256 entries in length.) A page table entry may be pointed to by the FRMPTE field of a frame table entry if a frame is associated with the page. Any specific page table entry can be obtained by extracting the page number (bits 12-19 for ESA390 and bits 44-51 for ESAME) from the vitrual address and, by multiplying the page number by the correct PTE length, calculating the offset into the page table. CREATED BY : HCPBPBCU HCPBPBIE HCPBPBIM HCPBPBSL A page table is imbedded in a page management block and consequently space for the PTE is created when the PGMBK is created. At initialization time, information for CP pagable initialization modules is put in PTEs by HCPISTOR. After initialization, the infromation within each PTE is filled in my HCPTRANS. DELETED BY : HCPRCIRL HCPRPBPA HCPRPBPS HCPRPBRM HCPRPBSL A page table is deleted when a page management block is released.
PAGTE Control Block Content
PAGTE DSECT
Hex Dec Type/Val Lng Label (dup) Comments ---- ---- --------- ---- -------------- -------- 0000 0 Structure PAGTE Page Table Entry ESA/390 mode Page-Table Entry format 0000 0 Signed 4 PAGENTRY HARDWARE PAGE TABLE ENTRY PAGENTRY PAGPFRAM X'7FFFF000' Isolate page-frame-real address PAGENTRY PAGPTOM X'7FFFFC00' Isolate Page Table Origin (PTO) given the address of a PTE PAGENTRY PAGINVM X'00000400' Isolate page-invalid bit PAGENTRY PAGPROTM X'00000200' Isolate page-protection bit PAGENTRY PAGRSVM X'80000900' Reserved bits, must be 0 in any valid PTE 00000004 PAGLENTH *-PAGENTRY LENGTH OF ONE PAGE TABLE ENTRY 0004 4 Signed 4 PAGNEXT (0) NEXT PAGE TABLE ENTRY 0000 0 Bitstring 1 * BITS 1-19 ARE ARCHITECTED AS THE 0001 1 Bitstring 1 * 4K ALIGNED PAGE FRAME ADDRESS. 0002 2 Bitstring 1 PAGSTAT BITS 0, 20, AND 23 MUST BE ZERO, BITS 21 AND 22 ARE DEFINED BELOW. .... .1.. PAGINVAL X'04' PAGE TABLE ENTRY IS INVALID .... ..1. PAGPROT X'02' PAGE PROTECTED (READ ONLY) The following definitions are for Minidisk cache virtual address space data pages. MDC uses these bits rather than the ones in the PGSTE because MDC uses compact page tables (4 page tables per frame). .... ...1 PAGXSVAL X'01' Indicates that an invalid MDC PTE is valid in XSTORE. 0003 3 Bitstring 1 PAGSTAT2 Second status byte .... .1.. PAGXSREF X'04' Indicates that the XSTORE block has been referenced. The following maps the page-table entry in the System/370 architecture. Note that System/370 page-table entries are only two bytes long; these mask definitions assume that the two byte System/370 PTE value is loaded into the rightmost two bytes of a GPR. 0000FFF0 PAG3PF4M X'0000FFF0' Isolate page-frame-real address for S/370 PTE, 4K pages .... 1... PAG3IN4M X'00000008' Isolate page-invalid bit for S/370 PTE, 4K pages .... .11. PAG3EA4M X'00000006' Isolate extended-storage-address bits for S/370 PTE, 4K pages 00FF0008 PAG3RS4M X'FFFF0008' Reserved bits, must be 0 in any valid S/370 PTE, 2K pages 0000FFF8 PAG3PF2M X'0000FFF8' Isolate page-frame-real address for S/370 PTE, 2K pages .... .1.. PAG3IN2M X'00000004' Isolate page-invalid bit for S/370 PTE, 2K pages 00FF0006 PAG3RS2M X'FFFF0006' Reserved bits, must be 0 in any valid S/370 PTE, 2K pages 00FF0001 PAG3B15M X'FFFF0001' S/370 PTE bit 15 is unassigned and not checked for *
PAGTE Storage Layout
*** PAGTE - Page Table Entry * * +---------------------------+ * 0 | PAGENTRY | * +---------------------------+ * *** PAGTE - Page Table Entry *** Overlay for PAGENTRY in PAGTE * * +------+------+------+------+ * 0 |//////|//////|:STAT |:STAT2| 4 * +------+------+------+------+ * *** Overlay for PAGENTRY in PAGTE
PAGTE Cross Reference
Symbol Dspl Value -------------- ---- ----- PAGENTRY 0000 PAGINVAL 0002 04 PAGINVM 0000 PAGENTRY PAGLENTH 0000 00000004 PAGNEXT 0004 PAGPFRAM 0000 PAGENTRY PAGPROT 0002 02 PAGPROTM 0000 PAGENTRY PAGPTOM 0000 PAGENTRY PAGRSVM 0000 PAGENTRY PAGSTAT 0002 PAGSTAT2 0003 PAGXSREF 0003 04 PAGXSVAL 0002 01 PAG3B15M 0003 00FF0001 PAG3EA4M 0003 06 PAG3IN2M 0003 04 PAG3IN4M 0003 08 PAG3PF2M 0003 0000FFF8 PAG3PF4M 0003 0000FFF0 PAG3RS2M 0003 00FF0006 PAG3RS4M 0003 00FF0008
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