Programming Interface Information: This information is NOT intended to be
used as Programming Interfaces of z/VM.

PAG64

Prolog  

Control Block Contents  
   PAG64 DSECT

Storage Layout  

Cross Reference (Contains links to field and bit definitions)  


 

PAG64 Control Block Content


PAG64 DSECT

Hex   Dec Type/Val   Lng Label (dup)    Comments
---- ---- --------- ---- -------------- --------
0000    0 Structure      PAG64          Page Table Entry
0000    0 Dbl-Word     8 PAGGENTR       PTEs are 8 bytes in ESAME
     PAGGPTOM = X'FFFFFFFFFFFFF800' represents the mask that could be used
     to isolate Page Table Origin (PTO) given the address of a PTE. 64-bit
     mask X'FFFFFFFFFFFFF800'
          00FFFFFF       PAGGPTMH       X'FFFFFFFF' Isolate high half of
                                        PTOM
          00FFF800       PAGGPTML       X'FFFFF800' Isolate low half of
                                        PTOM
     PAGGPFRA = X'FFFFFFFFFFFFF000' represents the mask that could be used
     to isolate the Page Frame Real Address from the address of a known PTE.
     NOTE that an instance of this constant exists at PFXGPFRA. 64-bit mask
     X'FFFFFFFFFFFFF000'
          00FFFFFF       PAGGPFAH       X'FFFFFFFF' Isolate high half of
                                        PFRA
          00FFF000       PAGGPFAL       X'FFFFF000' Isolate low half of
                                        PFRA
     64-bit mask X'0000000000000400' 32-bit high X'00000000' High half of
     mask
          00000400       PAGGINVR       X'00000400' Isolate I bit
     64-bit mask X'0000000000000200' 32-bit high X'00000000' High half of
     mask
          00000200       PAGGPROR       X'00000200' Isolate P bit
     64-bit mask X'0000000000000001' 32-bit high X'00000000' High half of
     mask
          .... ...1      PAGGLOKR       X'00000001' Isolate L bit
     64-bit mask X'00000000000000FE' 32-bit high X'00000000' High half of
     mask
          1111 111.      PAGGRSDR       X'000000FE' Reserved for IBM use
     64-bit mask X'0000000000000900' 32-bit high X'00000000' High half of
     mask
          00000900       PAGGRSVR       X'00000900' Reserved bits, must
                                        be 0 in any valid ESAME PTE
     The following equates may only be used when the PTE is invalid (the PTE
     I bit is set, meaning the page is not valid in host real storage):
     64-bit mask X'0000000000000100' 32-bit high X'00000000' High half of
     mask
          00000100       PAGGXVXR       X'00000100' Isolate V bit (valid
                                        in expanded storage, only
                                        meaningful if I bit is also set)
     64-bit mask X'0000000000000500' 32-bit high X'00000000' High half of
     mask
          00000500       PAGGXIVR       X'00000500' Isolate I bit *AND* V
                                        bit together
     64-bit mask X'FFFFFFFF00000000'
          00FFFFFF       PAGGXBNH       X'FFFFFFFF' Isolate XSBN
          .... ....      PAGGXBNL       X'00000000' Low half of mask
          00000000       PAGGXBNBL      0 Number of bits to the left of
                                        the XSBN. Can be used for
                                        shifting.
          00000020       PAGGXBNBR      32 Number of bits to the right of
                                        the XSBN. Can be used for
                                        shifting.
     64-bit mask X'00000000000000F0' 32-bit high X'00000000' High half of
     mask
          1111 ....      PABBCACR       X'000000F0' Isolate Xstore access
                                        control bits
     64-bit mask X'0000000000000008' 32-bit high X'00000000' High half of
     mask
          .... 1...      PAGGXSFR       X'00000008' Isolate Xstore F bit
                                        (Fetch-protection bit)
     64-bit mask X'0000000000000004' 32-bit high X'00000000' High half of
     mask
          .... .1..      PAGGXSRR       X'00000004' Isolate Xstore R bit
                                        (Reference bit)
     64-bit mask X'0000000000000002' 32-bit high X'00000000' High half of
     mask
          .... ..1.      PAGGXSCR       X'00000002' Isolate Xstore C bit
                                        (Change bit)
     64-bit mask X'0000000000000001' 32-bit high X'00000000' High half of
     mask
          .... ...1      PAGGXSLR       X'00000001' Isolate Xstore L bit
                                        (Lock bit)
     64-bit mask X'0000000000000800' 32-bit high X'00000000' High half of
     mask
          00000800       PAGGXIGR       X'00000800' Bit is ignored
                                        (available for CP programming
                                        use) if PTE is valid in xstore
     The following equates may only be used when the PTE is invalid in both
     host real and expanded storage (the PTE I bit is 1 and the Valid in
     Xstore bit, bit 55, is 0). Probably want to leave the P bit, the L bit
     and also the xstore status bits alone...
     64-bit mask X'FFFFFFFFFFFFFAFF'
          00FFFFFF       PAGGIRSH       X'FFFFFFFF' Reserved bits, high
                                        half
          00FFFAFF       PAGGIRSL       X'FFFFFAFF' Reserved bits, low
                                        half
0000    0 Signed       4 PAG64W0 (0)    ESAME PTE Word 0
0000    0 Signed       4 PAGGPFRL       Bits 0-32 of 64 bit PFRA
0004    4 Signed       4 PAG64W1 (0)    ESAME PTE Word 1
0004    4 Signed       4 PAGGPFRR       Bits 32-51 of 64 bit PFRA, plus
                                        12 status bits
          00000008       PAGGLENG       *-PAGGENTR Length of one page
                                        table entry
0008    8 Signed       4 PAGGNEXT (0)   Next page table entry
0000    0 Signed       4 *              Architected as bits 0-31 of the
                                        4K aligned page frame real
                                        address (if valid in storage), or
                                        20 programming bits and bits 0-11
                                        of the xstore block number (if
                                        valid in xstore)
0004    4 Signed       2 *              Architected as bits 32-47 of the
                                        4K aligned page frame real
                                        address (if valid in storage), or
                                        bits 12-27 of the xstore block
                                        number (if valid in xstore)
0006    6 Bitstring    1 PAGGSTAT       Architected as bits 48-51 of the
                                        4K aligned page frame real
                                        address (if valid in storage), or
                                        bits 28-31 of the xstore block
                                        number (if valid in xstore),
                                        followed by four flag bits:
          1111 ....      PAGGSPFR       X'F0' Bits 48-51 of PFRA (if
                                        valid) or bits 28-31 of XSBN (if
                                        valid in xstore)
          .... 1..1      PAGGSMBZ       X'09' Must be zero in any valid
                                        PTE
          .... .1..      PAGGINVA       X'04' Page-Table Entry is invalid
          .... ..1.      PAGGPROT       X'02' Page protected (read only)
          .... .1.1      PAGGSXVA       X'05' Page is invalid, but is
                                        valid in xstore
          .... 1...      PAGGSIVX       X'08' Bit is ignored if PTE is
                                        valid in xstore
0007    7 Bitstring    1 PAGGSTA2       Contains 7 reserved bits plus L-
                                        bit (for LKPG) if PTE is valid,
                                        or Access Control, Fetch protect,
                                        reference and change bits plus L-
                                        bit if PTE is valid in Xstore.
          1111 111.      PAGGS2PG       X'FE' Reserved bits if PTE is
                                        valid
          .... ...1      PAGGS2LK       X'01' Lock bit (used by LKPG)
          1111 ....      PAGGS2XA       X'F0' Access Control bits if PTE
                                        is invalid, but valid in xstore
          .... 1...      PAGGS2XF       X'08' F (Fetch-protection) bit if
                                        PTE is invalid, but valid in
                                        xstore
          .... .1..      PAGGS2XR       X'04' R (Reference) bit if PTE is
                                        invalid, but valid in xstore
          .... .1..      PAGGS2XC       X'04' C (Change) bit if PTE is
                                        invalid, but valid in xstore
          .... ...1      PAGGS2XL       X'01' L (Lock) bit if PTE is
                                        invalid, but valid in xstore
0000    0 Signed       4 PAGGXSBN       Xstore block number. Only valid
                                        when PTE is invalid and PGSXSTOR
                                        is set in corresponding PGSTE.
                                        For MDC PTEs, only valid when PTE
                                        is invalid in real storage, but
                                        valid in xstore.
0004    4 Signed       4 *              Reserved for IBM use
     Note that in the ESAME PTE format, unlike the ESA/390 PTE format, we
     use the same layout for MDC PTEs as for all other PTEs.
     *

 

PAG64 Storage Layout

          
*** PAG64 - Page Table Entry
*
*     +-------------------------------------------------------+
*   0 |                       PAGGENTR                        |
*     +-------------------------------------------------------+
*   8
*
*** PAG64 - Page Table Entry
          
*** Overlay for PAGGENTR in PAG64
*
*     +---------------------------+---------------------------+
*   0 |         PAGGPFRL          |         PAGGPFRR          |
*     +---------------------------+---------------------------+
*
*** Overlay for PAGGENTR in PAG64
          
*** Overlay for PAGGENTR in PAG64
*
*     +---------------------------+-------------+------+------+
*   0 |///////////////////////////|/////////////|:GSTAT|:GSTA2|
*     +---------------------------+-------------+------+------+
*   8
*
*** Overlay for PAGGENTR in PAG64
          
*** Overlay for PAGGENTR in PAG64
*
*     +---------------------------+---------------------------+
*   0 |         PAGGXSBN          |///////////////////////////|
*     +---------------------------+---------------------------+
*   8
*
*** Overlay for PAGGENTR in PAG64

 

PAG64 Cross Reference

Symbol         Dspl Value
-------------- ---- -----
PABBCACR       0000 F0
PAGGENTR       0000
PAGGINVA       0006 04
PAGGINVR       0000 00000400
PAGGIRSH       0000 00FFFFFF
PAGGIRSL       0000 00FFFAFF
PAGGLENG       0004 00000008
PAGGLOKR       0000 01
PAGGNEXT       0008
PAGGPFAH       0000 00FFFFFF
PAGGPFAL       0000 00FFF000
PAGGPFRL       0000
PAGGPFRR       0004
PAGGPROR       0000 00000200
PAGGPROT       0006 02
PAGGPTMH       0000 00FFFFFF
PAGGPTML       0000 00FFF800
PAGGRSDR       0000 FE
PAGGRSVR       0000 00000900
PAGGSIVX       0006 08
PAGGSMBZ       0006 09
PAGGSPFR       0006 F0
PAGGSTAT       0006
PAGGSTA2       0007
PAGGSXVA       0006 05
PAGGS2LK       0007 01
PAGGS2PG       0007 FE
PAGGS2XA       0007 F0
PAGGS2XC       0007 04
PAGGS2XF       0007 08
PAGGS2XL       0007 01
PAGGS2XR       0007 04
PAGGXBNBL      0000 00000000
PAGGXBNBR      0000 00000020
PAGGXBNH       0000 00FFFFFF
PAGGXBNL       0000 00
PAGGXIGR       0000 00000800
PAGGXIVR       0000 00000500
PAGGXSBN       0000
PAGGXSCR       0000 02
PAGGXSFR       0000 08
PAGGXSLR       0000 01
PAGGXSRR       0000 04
PAGGXVXR       0000 00000100
PAG64W0        0000
PAG64W1        0004

This information is based on z/VM V4R1.0.
Last updated on 6 Jun 2001 at 12:45:29 EDT.
Copyright IBM Corporation, 1990, 2001